LM3S5P36 Datasheet, PDF (3/1050 Pages) Texas Instruments – Stellaris® LM3S5P36 Microcontroller

Stellaris^® LM3S5P36 Microcontroller
Table of Contents
Revision History ............................................................................................................................. 32
About This Document .................................................................................................................... 41
Audience .............................................................................................................................................. 41
About This Manual ................................................................................................................................ 41
Related Documents ............................................................................................................................... 41
Documentation Conventions .................................................................................................................. 42
1
1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.3.8
1.4
Architectural Overview .......................................................................................... 44
Overview ...................................................................................................................... 44
Target Applications ........................................................................................................ 46
Features ....................................................................................................................... 46
ARM Cortex-M3 Processor Core .................................................................................... 46
On-Chip Memory ........................................................................................................... 48
Serial Communications Peripherals ................................................................................ 49
System Integration ........................................................................................................ 53
Advanced Motion Control ............................................................................................... 59
Analog .......................................................................................................................... 61
JTAG and ARM Serial Wire Debug ................................................................................ 62
Packaging and Temperature .......................................................................................... 63
Hardware Details .......................................................................................................... 63
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.5
2.5.1
2.5.2
2.5.3
The Cortex-M3 Processor ...................................................................................... 64
Block Diagram .............................................................................................................. 65
Overview ...................................................................................................................... 66
System-Level Interface .................................................................................................. 66
Integrated Configurable Debug ...................................................................................... 66
Trace Port Interface Unit (TPIU) ..................................................................................... 67
Cortex-M3 System Component Details ........................................................................... 67
Programming Model ...................................................................................................... 68
Processor Mode and Privilege Levels for Software Execution ........................................... 68
Stacks .......................................................................................................................... 68
Register Map ................................................................................................................ 69
Register Descriptions .................................................................................................... 70
Exceptions and Interrupts .............................................................................................. 83
Data Types ................................................................................................................... 83
Memory Model .............................................................................................................. 83
Memory Regions, Types and Attributes ........................................................................... 85
Memory System Ordering of Memory Accesses .............................................................. 85
Behavior of Memory Accesses ....................................................................................... 86
Software Ordering of Memory Accesses ......................................................................... 86
Bit-Banding ................................................................................................................... 87
Data Storage ................................................................................................................ 90
Synchronization Primitives ............................................................................................. 90
Exception Model ........................................................................................................... 91
Exception States ........................................................................................................... 92
Exception Types ............................................................................................................ 92
Exception Handlers ....................................................................................................... 95
January 21, 2012
3
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