LM3S5P36 Datasheet, PDF (644/1050 Pages) Texas Instruments – Stellaris® LM3S5P36 Microcontroller

Universal Asynchronous Receivers/Transmitters (UARTs)
Register 14: UART DMA Control (UARTDMACTL), offset 0x048
The UARTDMACTL register is the DMA control register.
UART DMA Control (UARTDMACTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x048
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DMAERR TXDMAE RXDMAE
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:3
2
Name
reserved
DMAERR
Type
Reset Description
RO 0x00000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0
DMA on Error
Value Description
1 µDMA receive requests are automatically disabled when a
receive error occurs.
0 µDMA receive requests are unaffected when a receive error
occurs.
1
TXDMAE
R/W
0
Transmit DMA Enable
Value Description
1 µDMA for the transmit FIFO is enabled.
0 µDMA for the transmit FIFO is disabled.
0
RXDMAE
R/W
0
Receive DMA Enable
Value Description
1 µDMA for the receive FIFO is enabled.
0 µDMA for the receive FIFO is disabled.
644
January 21, 2012
Texas Instruments-Production Data