LM3S5P36 Datasheet, PDF (465/1050 Pages) Texas Instruments – Stellaris® LM3S5P36 Microcontroller

Stellaris^® LM3S5P36 Microcontroller
10.3.3
10.3.4
10.4
DMA Operation
The timers each have a dedicated μDMA channel and can provide a request signal to the μDMA
controller. The request is a burst type and occurs whenever a timer raw interrupt condition occurs.
The arbitration size of the μDMA transfer should be set to the amount of data that should be
transferred whenever a timer event occurs.
For example, to transfer 256 items, 8 items at a time every 10 ms, configure a timer to generate a
periodic timeout at 10 ms. Configure the μDMA transfer for a total of 256 items, with a burst size of
8 items. Each time the timer times out, the μDMA controller transfers 8 items, until all 256 items
have been transferred.
No other special steps are needed to enable Timers for μDMA operation. Refer to “Micro Direct
Memory Access (μDMA)” on page 346 for more details about programming the μDMA controller.
Accessing Concatenated Register Values
The GPTM is placed into concatenated mode by writing a 0x0 or a 0x1 to the GPTMCFG bit field in
the GPTM Configuration (GPTMCFG) register. In both configurations, certain registers are
concatenated to form pseudo 32-bit registers. These registers include:
■ GPTM Timer A Interval Load (GPTMTAILR) register [15:0], see page 488
■ GPTM Timer B Interval Load (GPTMTBILR) register [15:0], see page 489
■ GPTM Timer A (GPTMTAR) register [15:0], see page 496
■ GPTM Timer B (GPTMTBR) register [15:0], see page 497
■ GPTM Timer A Value (GPTMTAV) register [15:0], see page 498
■ GPTM Timer B Value (GPTMTBV) register [15:0], see page 499
■ GPTM Timer A Match (GPTMTAMATCHR) register [15:0], see page 490
■ GPTM Timer B Match (GPTMTBMATCHR) register [15:0], see page 491
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
Likewise, a 32-bit read access to GPTMTAR returns the value:
GPTMTBR[15:0]:GPTMTAR[15:0]
A 32-bit read access to GPTMTAV returns the value:
GPTMTBV[15:0]:GPTMTAV[15:0]
Initialization and Configuration
To use a GPTM, the appropriate TIMERn bit must be set in the RCGC1 register (see page 262). If
using any CCP pins, the clock to the appropriate GPIO module must be enabled via the RCGC1
register (see page 262). To find out which GPIO port to enable, refer to Table 22-4 on page 976.
Configure the PMCn fields in the GPIOPCTL register to assign the CCP signals to the appropriate
pins (see page 441 and Table 22-5 on page 980).
January 21, 2012
465
Texas Instruments-Production Data