LM3S5P36 Datasheet, PDF (621/1050 Pages) Texas Instruments – Stellaris® LM3S5P36 Microcontroller

Stellaris^® LM3S5P36 Microcontroller
Register 3: UART Flag (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1.
UART Flag (UARTFR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x018
Type RO, reset 0x0000.0090
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TXFE RXFF TXFF RXFE BUSY
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
Bit/Field
31:8
7
Name
reserved
TXFE
Type
RO
RO
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
UART Transmit FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
1 If the FIFO is disabled (FEN is 0), the transmit holding register
is empty.
If the FIFO is enabled (FEN is 1), the transmit FIFO is empty.
0 The transmitter has data to transmit.
6
RXFF
RO
0
UART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
1 If the FIFO is disabled (FEN is 0), the receive holding register
is full.
If the FIFO is enabled (FEN is 1), the receive FIFO is full.
0 The receiver can receive data.
January 21, 2012
621
Texas Instruments-Production Data