LM3S5P36 Datasheet, PDF (11/1050 Pages) Texas Instruments – Stellaris® LM3S5P36 Microcontroller

Stellaris^® LM3S5P36 Microcontroller
List of Figures
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Stellaris LM3S5P36 Microcontroller High-Level Block Diagram ............................... 45
CPU Block Diagram ............................................................................................. 66
TPIU Block Diagram ............................................................................................ 67
Cortex-M3 Register Set ........................................................................................ 69
Bit-Band Mapping ................................................................................................ 89
Data Storage ....................................................................................................... 90
Vector Table ........................................................................................................ 96
Exception Stack Frame ........................................................................................ 98
SRD Use Example ............................................................................................. 112
JTAG Module Block Diagram .............................................................................. 173
Test Access Port State Machine ......................................................................... 176
IDCODE Register Format ................................................................................... 182
BYPASS Register Format ................................................................................... 182
Boundary Scan Register Format ......................................................................... 183
Basic RST Configuration .................................................................................... 187
External Circuitry to Extend Power-On Reset ....................................................... 187
Reset Circuit Controlled by Switch ...................................................................... 188
Power Architecture ............................................................................................ 191
Main Clock Tree ................................................................................................ 194
Hibernation Module Block Diagram ..................................................................... 284
Using a Crystal as the Hibernation Clock Source ................................................. 286
Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 287
Internal Memory Block Diagram .......................................................................... 309
μDMA Block Diagram ......................................................................................... 347
Example of Ping-Pong μDMA Transaction ........................................................... 353
Memory Scatter-Gather, Setup and Configuration ................................................ 355
Memory Scatter-Gather, μDMA Copy Sequence .................................................. 356
Peripheral Scatter-Gather, Setup and Configuration ............................................. 358
Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 359
Digital I/O Pads ................................................................................................. 407
Analog/Digital I/O Pads ...................................................................................... 408
GPIODATA Write Example ................................................................................. 409
GPIODATA Read Example ................................................................................. 409
GPTM Module Block Diagram ............................................................................ 456
Timer Daisy Chain ............................................................................................. 460
Input Edge-Count Mode Example ....................................................................... 462
16-Bit Input Edge-Time Mode Example ............................................................... 463
16-Bit PWM Mode Example ................................................................................ 464
WDT Module Block Diagram .............................................................................. 501
Implementation of Two ADC Blocks .................................................................... 526
ADC Module Block Diagram ............................................................................... 527
ADC Sample Phases ......................................................................................... 530
Doubling the ADC Sample Rate .......................................................................... 531
Skewed Sampling .............................................................................................. 531
Sample Averaging Example ............................................................................... 532
January 21, 2012
11
Texas Instruments-Production Data