LM3S5P36 Datasheet, PDF (69/1050 Pages) Texas Instruments – Stellaris® LM3S5P36 Microcontroller

Stellaris^® LM3S5P36 Microcontroller
2.3.3
the main stack and the process stack, with a pointer for each held in independent registers (see the
SP register on page 72).
In Thread mode, the CONTROL register (see page 82) controls whether the processor uses the
main stack or the process stack. In Handler mode, the processor always uses the main stack. The
options for processor operations are shown in Table 2-1 on page 69.
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use
Processor Mode
Use
Thread
Applications
Handler
Exception handlers
a. See CONTROL (page 82).
Privilege Level
Privileged or unprivileged ^a
Always privileged
Stack Used
Main stack or process stack ^a
Main stack
Register Map
Figure 2-3 on page 69 shows the Cortex-M3 register set. Table 2-2 on page 70 lists the Core
registers. The core registers are not memory mapped and are accessed by register name, so the
base address is n/a (not applicable) and there is no offset.
Figure 2-3. Cortex-M3 Register Set
Low registers
High registers
Stack Pointer
Link Register
Program Counter
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
SP (R13)
LR (R14)
PC (R15)
PSR
PRIMASK
FAULTMASK
BASEPRI
CONTROL
General-purpose registers
PSP^‡
MSP^‡
Program status register
Exception mask registers
CONTROL register
‡_{Banked version of SP}
Special registers
January 21, 2012
69
Texas Instruments-Production Data