CDC960 Datasheet, PDF (8/38 Pages) Texas Instruments – 200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE

CDC960
200ĆMHz CLOCK SYNTHESIZER/DRIVER
WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE
SCAS675 – APRIL 2002
power-up sequences
Sampled inputs are: FS0, FS1, FS2 and 24/48_SEL.
State S1 is an analog controlled delay derived from internal reference voltages to ensure that a valid input state
is captured. There is no specific delay in this state after power up.
Figure 3 shows the symbolic sequence of the CDC960 during power up. States S0–S4 are required to ensure
proper configuration and operation of the device functions.
Outputs Disabled
VDD ≤ 2 V
Outputs
Undefined
S1
Delay
S2
Sample
Input Straps
S0
Power Off
VDD = Off
S4
Normal
Operation
S3
Power Up
Wait
3 ms
Enable
Outputs
Figure 3. Power-Up State Transitions
SMBus serial interface
The following section describes the SMBus interface programming.
In general the CDC960 SMBus protocol supports only block write and block read operations.
SMBus device address
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
0
0 = write to CDC960
1 = read from CDC960
writing to the SMBus interface
1. Send the address D2_(H) and validate the acknowledge from the slave.
2. Send the dummy byte as a command code and validate the acknowledge from the slave.
3. Send the number of data bytes to write and validate the acknowledge from the slave.
4. Write the desired data bytes to registers and validate the acknowledge from the slave for each data byte.
Clock Generator
Addr (7 bits)
A(6:0) & R/W
ACK
+8 bits dummy
command code
ACK
+8 bits byte
count
ACK
Data byte 0
ACK Data byte N ACK
D2(H)
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