CDC960 Datasheet, PDF (11/38 Pages) Texas Instruments – 200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE

CDC960
200ĆMHz CLOCK SYNTHESIZER/DRIVER
WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE
SCAS675 – APRIL 2002
SMBus configuration command bitmap (continued)
Byte 2: PCI Clock USB FDC and REF Control Register
(H = Enable, L = Disable)
BIT TYPE
PUD^†
DESCRIPTION
PIN AFFECTED
(WRITE OPERATION)
SOURCE PIN
(READ OPERATION)
7
R/W
H
CPU1 enable‡
36, 37
Register value
6
R/W
H
CPU0 enable‡
40, 41
Register value
5
R/W
H
REF2 enable
45
Register value
4
R/W
H
REF1 enable
48
Register value
3
R/W
H
REF0 enable
1
Register value
2
R/W
H
FDC (24_48 MHz) enable
28
Register value
1
R/W
H
USB enable
31
Register value
0
R/W
H
PCI/LDT2 enable
11
Register value
† _{PUD = Power-up condition}
‡ _{If a CPU clock is disabled by setting its control bit (bit 6 or bit 7) low, both the CPU and CPU outputs for the disabled clock are set low.}
Byte 3: PCI Clock Free Running Control Register (H = Free running, L = controlled by PCI_Stop/LDT_Stop))
BIT TYPE
PUD^†
DESCRIPTION
PIN AFFECTED
(WRITE OPERATION)
SOURCE PIN
(READ OPERATION)
7
R/W
L
PCI/LDT1 free-running enable^§
8
Register value
6
R/W
L
PCI/LDT0 free-running enable^§
7
Register value
5
R/W
L
PCI5 free-running enable^§
22
Register value
4
R/W
L
PCI4 free-running enable^§
21
Register value
3
R/W
L
PCI3 free-running enable^§
18
Register value
2
R/W
L
PCI2 free-running enable^§
17
Register value
1
R/W
L
PCI1 free-running enable^§
14
Register value
0
R/W
L
PCI0 free-running enable^§
13
Register value
† _{PUD = Power-up condition}
§ _{The above individual free-running enable/disable controls are intended to allow individual clock outputs to be made free running. A clock output}
that has its free-running bit enabled (set to H) is not turned off with the assertion of either PCI_Stop or LDT_Stop. If a particular bit is disabled
in Byte1, the Byte1 settings overwrite the Byte3 settings.
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