CDC960 Datasheet, PDF (24/38 Pages) Texas Instruments – 200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE

CDC960
200ĆMHz CLOCK SYNTHESIZER/DRIVER
WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE
SCAS675 – APRIL 2002
switching characteristics, V_DD = 3.135 V to 3.465 V, T_A = 0°C to 70°C (continued)
USB, FDC (48 MHz) and FDC (24 MHz), C_L = 20 pF, (USB) R_L = 500 Ω
PARAMETER
FROM
TO
(INPUT) (OUTPUT)
TEST CONDITIONS
MIN TYP^†
tpd1
Propagation delay time
XIN
USB/FDC f(XIN) ≥ 1 MHz, TEST MODE
2
tpd2
Propagation delay time
SCLK↑ USB/FDC TEST MODE
USB/FDC (48 MHz) clock period^‡
tc
FDC (24 MHz) clock period^‡
f(USB/FDC) = 48 MHz
f(FDC) = 24 MHz
18
20.8
41.6
tjit(cc)
Cycle to cycle jitter FDC (48 MHz) or FDC (24 MHz)
Cycle to cycle jitter USB (48 MHz), FDC=24 or 48 MHz
f(CPU) = 100 to 200 MHz
f(CPU) = 100 to 200 MHz
tjit(acc) Accumulated jitter USB (48 MHz), FDC=24 or 48 MHz
f(CPU) = 100 to 200 MHz
–160
Duty cycle USB/FDC
odc
Duty cycle FDC
f(USB/FDC) = 48 MHz
45
f(FDC) = 24 MHz
45
tsk(ow)
USB to FDC skew ↑ edges
time-independent and
time-variant skew combined
USB
FDC
f(USB/FDC) = 48 MHz
f(USB/FDC) = 48 / 24 MHz
tsk(p)
t _w(H)
USB/FDC pulse skew
FDC pulse skew
Pulse duration, high
t _w(L) Pulse duration, low
tr
Rise time
USB/FDC USB/FDC f(USB/FDC) = 48 MHz
2
FDC
FDC
f(FDC) = 24 MHz
2
f(USB/FDC) = 48 MHz
7.5
f(FDC) = 24 MHz
18
f(USB/FDC) = 48 MHz
11.5
f(FDC) = 24 MHz
22
USB
1.1
FDC
Vref = 20% to 80% of VO
2
tf
Fall time
USB
1.1
FDC
Vref = 20% to 80% of VO
2
Edge rate, rising edge (maintained during total
USB
vr
transition)
FDC
Vref = 20% to 60% of VDD
0.25
vf
Edge rate falling edge (maintained during total
transition)
USB
FDC
Vref = 20% to 60% of VDD
0.25
† _{All typical values are measured at their nominal VDD values.}
‡ _{The average over any 1-µs period of time is greater than the minimum specified period}
MAX
15
20.84
41.68
200
180
160
55
55
500
500
6.5
6.5
2.5
0.7
2.5
0.7
1.1
1.1
UNIT
ns
ns
ns
ps
ps
%
ps
ns
ns
ns
ns
V/ns
ns
V/ns
V/ns
V/ns
24
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