CDC960 Datasheet, PDF (25/38 Pages) Texas Instruments – 200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE

CDC960
200ĆMHz CLOCK SYNTHESIZER/DRIVER
WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE
SCAS675 – APRIL 2002
switching characteristics, V_DD = 3.135 V to 3.465 V, T_A = 0°C to 70°C (continued)
PCI, LDT (33 MHz), PCI_F and LDT (66 MHz), C_L = 30 pF, R_L = 500 Ω
PARAMETER
FROM
TO
(INPUT) (OUTPUT)
TEST CONDITIONS
MIN TYP^† MAX
tpd1
tpd2
tc
tjit(cc)
tjit(acc)
odc
tdc
tsk(b)
tsk(ow)
tsk(b)
Propagation delay time
Propagation delay time
XIN
SCLK↑
PCIx,LDT
PCIx, LDT
PCI clock period^†
Cycle-to-cycle jitter PCI/LDT (33 MHz), LDT (33 MHz)
Cycle-to-cycle jitter LDT (66 MHz), PCI (33 MHz)
Accumulated jitter PCI/LDT (33 MHz), LDT (66 MHz)
Duty cycle PCI (33 MHz)
Duty cycle LDT (66MHz)
PCI bank skew ↑ edges
time-independent (3.3 V)
PCI bank skew ↑ edges
time-variant skew
PCIx
PCIx
↑ edges to CPU x-point
time-independent (3.3 V)
↑ edges to CPU x-point
time-variant skew
PCIn
CPUx
LDT bank skew ↑ edges
time-independent (3.3 V)
LDTx
LDTx
LDT bank skew ↑ edges
time-variant skew
f(XIN) ≥ 1 MHz, Test mode
Test mode
f(PCI) = 33.3 MHz
f(LDT) = 66.7MHz
f(CPU) = 100 to 200 MHz
f(CPU) = 100 to 200 MHz
f(PCI) = 33.3 MHz
f(LDT) = 66.7 MHz
f(PCI) = 33.3 MHz
f(PCI) = 33.3 MHz
f(LDT) = 66.7 MHz
2.0
29.95
14.95
–300
45
45
15
18
30.3
15.15
170
290
300
55
55
500
200
500
200
500
200
↑ edges to CPU x-point
time-independent (3.3 V)
LDTx
CPUx
500
tsk(ow)
↑ edges to CPU x-point tim-
variant skew
LDTx
CPUx
f(LDT) = 66.7 MHz
200
† _{All typical values are measured at their nominal VDD values.}
‡ _{The average over any 1-µs period of time is greater than the minimum specified period}
UNIT
ns
ns
ns
ps
ps
%
%
ps
ps
ps
ps
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