CDC960 Datasheet, PDF (5/38 Pages) Texas Instruments – 200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE

CDC960
200ĆMHz CLOCK SYNTHESIZER/DRIVER
WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE
SCAS675 – APRIL 2002
Terminal Functions
TERMINAL
NAME
CPU[0:1],CPU[0:1]
NO.
41, 37
40, 36
FS[0:2] & REF[0:2]
1, 48, 45
GND
GNDA
GNDF
LDT_Stop
5, 10, 15,
20, 27, 30,
34, 39, 47
42
33
12
PCI[0:5]
PCI_F
PCI/LDT[0:2]
PCI/LDT_SEL
13, 14, 17,
18, 21, 22
23
7, 8, 11
6
PCI_Stop
24
SCLK
25
SDATA
26
SPREAD
44
USB
VDD
31
2, 9, 16,
19, 29, 35,
38, 46
I/O
DESCRIPTION
O 3.3-V, differential CPU clock outputs
CPU Clock Outputs 0 and 1: CPU push-pull true clock outputs of the differential pair
CPU Clock Outputs 0 and 1: CPU push-pull complementary clock outputs of the differential pair
I/O 3.3 V, 14.318-MHz clock outputs
Frequency Select inputs: Power–on strapping to set device operating frequency as described in
the Device Frequency Select Functions table. These inputs have 150-kΩ internal pullup resistors.
Low = 0, High = 1. 3.3-V reference clock outputs: Fixed clock output at 14.318 MHz
G Power Connection: Connected to VSS. Used to ground digital portions of the chip
G Analog GND: Connected to VSS through filter. Used to ground the main CPU-PLL on the chip
G Analog GND for 48-MHz PLL: Connected to VSS through filter. Used to ground the 48-MHz PLL on
the chip
I Control for 66-MHz PCI clocks: Active LOW control input to halt all 66-MHz PCI clocks except the
free-running clock. This input has a 150-kΩ internal pullup resistor. Once this input has been
asserted, PCI/LDT outputs if operating at 66-MHz must stop in the low state within 1 µs.
Low = stop, High = running
O 3.3-V PCI clock outputs divided down from CPU-PLL
3.3-V PCI clock outputs: PCI clocks operate at 33 MHz.
O 3.3-V, 33-MHz clocks divided down from CPU-PLL
3.3-V Free-Running PCI clock output: The free-running PCI clock pin operates at 33 MHz. The
free-running PCI clock is not turned off when PCI_Stop# is activated LOW.
O 3.3-V PCI 33-MHz or LDT 66-MHz outputs: This group of outputs is selectable between 33 MHz
and 66 MHz based upon the state of PCI/LDT_SEL. When running at 66 MHz these outputs are for
use as reference clocks to LDT devices.
I PCI 33-MHz/LDT 66-MHz Select: This input selects the output frequency of PCI/LDT outputs to
either 33 MHz or 66 MHz. This is a dedicated input pin to avoid corruption of the input state due to
PCI add-in cards that may have termination resistors on the input clocks. This input has a 150-kΩ
internal pullup resistor. Low = 66-MHz outputs, High = 33-MHz outputs
I 3.3-V LVTTL-compatible input for PCI_Stop active low
Control for 33-MHz PCI clocks: Active LOW control input to halt all 33-MHz PCI clocks except the
free-running clock. This input has a 150-kΩ internal pullup resistor. Once this input has been
asserted, the PCI outputs and PCI/LDT outputs operating at 33 MHz must stop in the low state
within 1 µs.
Low = stop, High = running
I SMBus compatible SCLK.
Clock pin for SMBus circuitry (SMBus revision 1.1). This input has an internal pull-up resistor of
150 kΩ. SCLK is a 3.6-V tolerant signal input. High impedance at power down is not supported.
I/O SMBus compatible SDATA
Data pin for SMBus circuitry (SMBus revision 1.1). This output is open drain and has an internal
pullup resistor of 150 kΩ. SDATA is a 3.6V tolerant signal IO. High impedance at power down is not
supported.
I Spread Spectrum Clocking Enable: Power-on strapping to set spread spectrum clocking as
enabled or disabled. This input allows the default spread spectrum clocking mode to be enabled or
disabled upon power up. This input has a 150-kΩ internal pullup resistor.
Low = disable, High = enable. Note that all Athlon and Hammer systems are recommended to use
SSC; therefore, the default of this pin is enabled and should only be turned off for debug and test
purposes.
O 3.3-V, fixed 48-MHz non-SSC clock output
3.3-V USB clock output: Fixed clock output at 48 MHz
P Power Connection: Connected to 3.3-V power supply. Used to supply digital portions of the chip
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