CDC960 Datasheet, PDF (10/38 Pages) Texas Instruments – 200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE

CDC960
200ĆMHz CLOCK SYNTHESIZER/DRIVER
WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE
SCAS675 – APRIL 2002
SMBus configuration command bitmap
Byte 0: Frequency and Spread Spectrum Control Register (see Note 1)
(H = Enable, L = Disable)
BIT TYPE
7 R/W
PUD^†
L
DESCRIPTION
Write disable (write once). A 1 written to this bit after a 1 has been written to
Byte0, Bit0 disables modification of all configuration registers until the de-
vice has been powered off.
Spread spectrum enable. This bit provides a software programmable con-
trol forspread spectrum clocking. The truth table for SSC is as follows:
PIN AFFECTED
(WRITE
OPERATION)
—
SOURCE PIN
(READ
OPERATION)
Register value
Spread (ext. Pin) Byte0, Bit6
SSC Function
6 R/W
L
L
L
Disabled
—
L
H
Enabled
H
L
Enabled
H
H
Enabled
5 R/W
L
FS4 (corresponds to frequency selection table)
—
4 R/W
L
FS3 (corresponds to frequency selection table)
—
3
R/W
Externally FS2 (corresponds to frequency selection table). If write is enabled, this bit
selected^‡ can be set differently than the power-up condition.
—
Register value
Register value
Register value
45 at power up
2
R/W
Externally FS1 (corresponds to frequency selection table). If write is enabled, this bit
selected^‡ can be set differently than the power-up condition.
—
48 at power up
1
R/W
Externally FS0 (corresponds to frequency selection table). If write is enabled, this bit
selected^‡ can be set differently than the power-up condition.
—
1 at power up
Write Enable. A 1 written to this bit after power up enables modification of all
configuration registers and subsequent 0s written to this bit disable modifi-
cation of all configuration registers except this single bit. Note that when a 1
0 R/W
L
has been written to Byte0, Bit 7, all modification is permanently disabled un-
—
Register value
til the device power cycles. Note also, that block write transactions to the
interface are completed. However, unless the interface has been previously
unlocked, the writes have no effect.
† _{PUD = Power-up condition}
‡ _{The value of this bit is according to level applied to corresponding device pin at power up.}
NOTE 1: Byte0, Bit0 controls the write enable status for the device SMBus. If a 1 is written to Byte0, Bit0, the SMBus registers are write enabled.
Once write has been enabled, a new block write protocol must be sent to the device to program the desired register values. Once after
power up a 1 is written to Byte0, Bit0, the device functionality is according to the settings of the different registers. E.g., the device function
table is according to setting of Bits[1…6] of Byte0 and other functions are according to corresponding SMBus register settings.
If a 0 is written to Byte0, Bit0, write is disabled and the device function is according to the previous settings of the last write cycle.
Byte 1: PCI Clock Control Register
(H = Enable, L = Disable)
BIT TYPE
PUD^†
7
R/W
H
6
R/W
H
5
R/W
H
4
R/W
H
3
R/W
H
2
R/W
H
1
R/W
H
0
R/W
H
† _{PUD = Power-up condition}
DESCRIPTION
PCI/LDT1 enable
PCI/LDT0 enable
PCI5 enable
PCI4 enable
PCI3 enable
PCI2 enable
PCI1 enable
PCI0 enable
PIN AFFECTED
(WRITE OPERATION)
8
7
22
21
18
17
14
13
SOURCE PIN
(READ OPERATION)
Register value
Register value
Register value
Register value
Register value
Register value
Register value
Register value
10
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