CDC960 Datasheet, PDF (33/38 Pages) Texas Instruments – 200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE

CDC960
200ĆMHz CLOCK SYNTHESIZER/DRIVER
WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE
SCAS675 – APRIL 2002
PARAMETER MEASUREMENT INFORMATION
Differential Impedance = 100 Ω
VDD = 2.5 V
VDD = 2.5 V
CPU
RS1 = 15 Ω
1%
CDC960
CPU
RS1 = 15 Ω
1%
3900 pF
TLA
NPO 10%
3900 pF
TLB
NPO 10%
TLC
169 Ω
1%
TLC
250 Ω
1%
TLD
CL = 5 pF
200 Ω
1%
TLD
Test Node
Clock
CL = 5 pF
250 Ω
1%
200 Ω
1%
Test Node
Clock
TLA = TLB: ZO = 60 Ω, L = 12.7 cm (750 ps)
TLC: ZO = 60 Ω, L = 1.27 cm (75 ps)
TLD: ZO = 60 Ω, L = ~3.43 cm (~180 ps)
RT1 = 50 Ω
RT2 = 50 Ω
Figure 10. Load Circuit and Voltage Waveforms for CPU Bus
correction for measurements at 50 Ω nodes
Voltage levels and readings are scaled for the voltage divider 200 Ω to 50 Ω versus all reads and reference levels
must be multiplied/divided by the fixed scale of five.
tsk(ow2)
tsk(ow1)
tsk(ow5)
Bank1
tsk(ow3)
1
Bank2
Bank2
2
Bank2
3
Bank2
4
tsk(ow4)
5
Bank2
6
Bank2
tsk(ow6)
MIN to MAX Output Skew
Figure 11. Bank and Output Skew; t_sk(owx): Output Skew Window and MIN-to-MAX Phase
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