CDC960 Datasheet, PDF (1/38 Pages) Texas Instruments – 200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE

CDC960
200ĆMHz CLOCK SYNTHESIZER/DRIVER
WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE
SCAS675 – APRIL 2002
D Generates Clocks for AMD-K8 Clawhammer
Desktop Systems
D Uses a 14.318-MHz Crystal Input to
Generate Multiple Output Frequencies
D Includes Spread Spectrum Clocking (SSC),
0.5% Downspread for Reduced EMI
D Power Management Control Terminals
D SMBus Serial Interface Provides Output
Enable and Control
D Low-Output Skew and Low Jitter for Clock
Distribution
D Operates From Single 3.3-V Supply
D Generates the Following Clocks:
– 2 CPU (3.3 V, 180° shifted pairs,
200/166/133/100 MHz)
– 6 PCI (3.3 V, 33 MHz)
– 1 PCI_F (3.3 V, 33 MHz)
– 3 REF (3.3 V, 14.318 MHz)
– 1 USB (3.3 V, 48 MHz)
– 1 FDC (3.3 V, 24 MHz or 48 MHz)
– 3 PCI/LDT^† (3.3 V, 33 MHz or 66 MHz)
D Packaged in 48-Pin SSOP Package
description
The CDC960 is a clock synthesizer/driver and
buffer that generates CPU, PCI, PCI/LDT, USB,
FDC, and REF system clock signals to support
PCs with an AMD-K8 Clawhammer-class system.
DL PACKAGE
(TOP VIEW)
FS0 & REF0 1
V_DD 2
XIN 3
XOUT 4
GND 5
PCI/LDT_SEL 6
PCI/LDT0 7
PCI/LDT1 8
V_DD 9
GND 10
PCI/LDT2 11
LDT_Stop 12
PCI0 13
PCI1 14
GND 15
V_DD 16
PCI2 17
PCI3 18
V_DD 19
GND 20
PCI4 21
PCI5 22
PCI_F 23
PCI_Stop 24
48 FS1 & REF1
47 GND
46 V_DD
45 FS2 & REF2
44 SPREAD
43 V_DDA
42 GNDA
41 CPU0
40 CPU0
39 GND
38 V_DD
37 CPU1
36 CPU1
35 V_DD
34 GND
33 GNDF
32 V_DDF
31 USB
30 GND
29 V_DD
28 24/48_SEL & FDC
27 GND
26 SDATA
25 SCLK
All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input can be provided
at the XIN input instead of a crystal. It is recommended to use the bypass mode of the internal oscillator in this
case. Two phase-locked loops (PLLs) are used to generate the host frequencies and 48-MHz clock frequencies.
On-chip loop filters and internal feedback eliminate the need for external components.
The device provides a standard mode (100 kbps) SMBus 1.1 serial interface for device control. The
implementation is as a slave with read and write capability. The device address is specified in the SMBus serial
interface device address table. Both SMBus inputs (SDATA and SCLK) provide integrated pullup resistors
(typically 150 kΩ).
Seven 8-bit SMBus registers provide individual enable control for each of the outputs. The controllable outputs
default to enabled at power up and can be placed in a disabled mode with a low-level output when a low-level
control bit is written to the control register. The registers must be accessed in sequential order (i.e., random
access of the registers not supported).
The CPU, PCI, PCI_F, LDT, FDC (24/48-MHz), and USB (48-MHz) clock outputs provide low-skew/low-jitter
clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected via control
inputs FS0, FS1, and FS2 at power-up preset condition.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†LDT _{is equivalent to HT66 shown on AMD specification.}
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2002, Texas Instruments Incorporated
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