CDC960 Datasheet, PDF (15/38 Pages) Texas Instruments – 200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE

CDC960
200ĆMHz CLOCK SYNTHESIZER/DRIVER
WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE
SCAS675 – APRIL 2002
spread spectrum clock (SSC) implementation for CDC960
Simultaneously switching at a fixed frequency generates a significant power peak at the selected frequency,
which in turn causes an EMI disturbance to the environment. The purpose of the internal frequency modulation
of the CPU-PLL is to distribute the energy to many different frequencies, thus reducing the power peak.
A typical characteristic for a single-frequency spectrum and a modulated-frequency spectrum is shown in
Figure 4.
Maximum Peak
∆
SSC
Non-SSC
δ of fnom
fnom
Figure 4. Frequency Power Spectrum With and Without the Use of SSC
The modulated spectrum has its distribution to the left side of the single-frequency spectrum, which indicates
a down-spread modulation.
The peak reduction depends on the modulation scheme and modulation profile. System performance and timing
requirements are the limiting factors for actual design implementations. The implementation is driven to keep
the average clock frequency close to its upper specification limit. The modulation amount is set to –0.5%.
In order to allow a downstream PLL to follow the frequency modulated signal, the bandwidth of the modulation
signal is limited in order to minimize SSC-induced tracking skew jitter.
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