CDC960 Datasheet, PDF (23/38 Pages) Texas Instruments – 200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE

CDC960
200ĆMHz CLOCK SYNTHESIZER/DRIVER
WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE
SCAS675 – APRIL 2002
CPU C_L = 10 pF, R_L = Test Load (see Note 9) (continued)
PARAMETER
TEST CONDITIONS
MIN TYP^† MAX Unit
VOD
Differential output voltage
Test load at ac
coupling node
including CPU load.
CPU to CPU
1.3
1.7 V
∆VOD_DC
Change in dc differential output
voltage
CPU to CPU
–15
15 mV
VOCM
∆VOCM
Common mode voltage
Change in common mode
voltage
CPU to CPU
CPU to CPU
1.3
1.4 V
–10
10 mV
V_{CM_AC}
Common mode voltages (MIN/
MAX)
CPU to CPU
1.0
1.4 V
vcross
Absolute cross point voltages
crosspoint (low and high)
Test load at ac
coupling node
including CPU load.
CPU and CPU
1.0
1.2 V
∆vcross
Variation of Vcross, rising edge
At ↑ CPU(x…n), (max-min)
90 mV
T∆vcross Total variation Vcross, all edges
At ↑ or ↓ CPU(x…n),(max-min)
140 mV
† _{The average over any 1-µs period of time is greater than the minimum specified period}
NOTES: 9. This specification does not include variations caused by K8 input resistor network or K8 _VDD voltage variations.
The common mode voltage is calculated as: (VOH+VOL)/2. See the measurement information section for details.
10. This applies also to CPU outputs.
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