CDC960 Datasheet, PDF (12/38 Pages) Texas Instruments – 200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE

CDC960
200ĆMHz CLOCK SYNTHESIZER/DRIVER
WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE
SCAS675 – APRIL 2002
SMBus configuration command bitmap (continued)
Byte 4: Pin Latched/Real Time State Control Register (see Note 2)
(H = Enable, L = Disable)
BIT TYPE
PUD^†
7
R/W
H
6
R
Externally
selected^‡§
DESCRIPTION
PCI_F enable
SPREAD actual pin state
PIN AFFECTED
(WRITE OPERATION)
23
SOURCE PIN
(READ OPERATION)
Register value
44
5
R
Externally
selected^‡
24/48_SEL pin power up latched state
28 at power up
4
R
Externally
selected^‡§
3
R
Externally
selected^‡
Externally
2
R
selected^‡
PCI/LDT_SEL actual pin state
FS2 power-up latched pin state
FS1 power-up latched pin state
6
45 at power up
48 at power up
1
R
Externally
selected^‡
FS0 power-up latched pin state
1 at power up
0
R/W
L
PCI/LDT2 free-running enable^¶
11
Register value
† _{PUD = Power-up condition}
‡ _{The value of this bit is determined by the level applied to the corresponding device pin at power up.}
§ _{If the SMBus is in read mode, and the byte-count byte is being sent, the device input pin is sampled again at the falling edge of SCLK at the same}
state as the acknowledge state for the byte count that is initiated by SCLK↓.
¶ _{The above individual free running enable/disable controls are intended to allow individual clock outputs to be made free running. A clock output}
that has its free-running bit enabled (set to H) is not turned off with the assertion of either PCI_Stop or LDT_Stop. If a particular bit is disabled
in Byte2, the Byte2 settings overwrite the Byte4 settings.
NOTE 2: Byte4 holds the power-up information for pins latched at power up. In the case that an unintentional write has been made to these bits
of Byte4, the SMBus write is ignored; the bits always return the power-up latched value during an SMBus read operation.
This does not relate to the bits which hold the actual (current) pin state. Those bits can not be overwritten by software in order to get
the hardware setting states back via software.
Byte 5: Vendor Identification Register
(H = Enable, L = Disable)
BIT TYPE
PUD^†
DESCRIPTION
PIN AFFECTED
(WRITE OPERATION)
SOURCE PIN
(READ OPERATION)
7
R
H
Manufacturer ID (MSB)
–
6
R
H
Manufacturer ID
–
5
R
H
Manufacturer ID, TI is shown for vendor ID = 111
–
4
R
L
Device revision ID (MSB)
–
3
R
L
Device revision ID
–
2
R
L
Device revision ID
–
1
R
L
Device revision ID
–
0
R
H
Device revision ID, device revision: 00001
–
† _{PUD = Power-up condition}
Returns H
Returns H
Returns H
Returns L
Returns L
Returns L
Returns L
Returns H
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