CDC960 Datasheet, PDF (17/38 Pages) Texas Instruments – 200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE

CDC960
200ĆMHz CLOCK SYNTHESIZER/DRIVER
WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE
SCAS675 – APRIL 2002
recommended operating conditions (see Notes 4 and 5)
MIN NOM^†
MAX UNIT
Supply voltages, VDD
High-level input voltage, VIH
Low-level input voltage, VIL
3.3 V
PCI_Stop, LDT_Stop, PCI/LDT_SEL, 24/48_SEL, FS0, FS1,
FS2, SPREAD
SDATA, SCLK (see Note 6)
XIN
PCI_Stop, LDT_Stop, PCI/LDT_SEL, 24/48_SEL, FS0, FS1,
FS2, SPREAD
SDATA, SCLK (see Note 6)
XIN
3.135
2
2.0
2.0
−0.3
−0.3
−0.3
3.465 V
VDD +0.3
VDD +0.3
V
VDD +0.3
0.8
1.08
V
0.5
Input Voltage, VI
PCI_Stop, LDT_Stop, PCI/LDT_SEL, 24/48_SEL, FS0, FS1,
FS2, SPREAD
−0.3
SDATA, SCLK (see Note 6)
−0.3
CPU
High-level output current, IOH USB, FDC, REF
PCI, LDT
VDD +0.3
V
VDD +0.3
−18
−12 mA
−12
CPU
18
Low-level output current, IOL
USB, FDC, REF
PCI, LDT
9
mA
9
SDATA
4
Input resistance to VDD, RI
PCI_Stop, LDT_Stop, PCI/LDT_SEL, 24/48_SEL, FS0, FS1,
FS2, SPREAD
100
SDATA, SCLK
100
220
kΩ
220
Reference frequency, f(XIN)^‡ PLL BY–PASS MODE
Crystal frequency, f(XTAL)^§
NORMAL MODE
SCLK frequency, f(SCLK)^¶
Bus free time, t(BUS)^¶
START setup time, tsu(START)^¶
START hold time, th(START)^¶
SCLK low pulse duration, tw(SCLL)^¶
SCLK high pulse duration, tw(SCLH)^¶
SDATA input rise time, tr(SDATA)^¶
SDATA input fall time, tf(SDATA)^¶
SDATA setup time, tsu(SDATA)^¶
0
10 14.31818
4.7
4.7
4.0
4.7
4.0
250
200
16
100
1000
300
MHz
MHz
kHz
µs
µs
µs
µs
µs
ns
ns
ns
SDATA hold time, th(SDATA)
5
ns
STOP setup time, tsu(STOP)^¶
4
µs
Operating free–air temperature, TA
0
70 °C
† _{All typical values are measured at their respective nominal VDD.}
‡ _{Reference frequency is a test clock driven on the XIN input during the device test mode and normal mode. In test mode, XIN can be driven}
externally up to f(XIN) = 0 MHz to 200 MHz. If XIN is driven externally, XOUT is floating.
§ _{This is a fundamental crystal with fO = 14.31818 MHz and 18 pF load in a parallel resonance application (Pierce-type oscillator)}
¶ _{This conforms to SMBus Specification, Version 1.1.}
NOTES: 4. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for the through-hole packages,
which use a trace length of zero. The absolute maximum power dissipation allowed at TA = 55^°C (in still air) is 1.0 W.
5. The maximum package power dissipation is calculated using a junction temperature of 150^°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002.
6. The CMOS-level inputs fall within these limits: VIHmin = 0.7 × VDD and VILmax = 0.3 × VDD.
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