CDC960 Datasheet, PDF (14/38 Pages) Texas Instruments – 200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE

CDC960
200ĆMHz CLOCK SYNTHESIZER/DRIVER
WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE
SCAS675 – APRIL 2002
SMBus configuration command bitmap (continued)
Byte 8: Vendor Specific Register (reserved)
BIT TYPE
PUD^†
DESCRIPTION
7
R/W
L
6
R/W
L
5
R/W
L
4
R/W
L
3
R/W
L
2
R/W
L
1
R/W
L
0
R/W
L
† _{PUD = Power-up condition}
Trigger single pulse at the L-to-H transition of this bit
after an SMBus write cycle completes. This bit must be
written back to L in order to trigger a following pulse with
a new L-to-H transition at the completion of a write
protocol.
Single-pulse ARM bit
H = enable, L = disable single-pulse feature
Must set to L during the byte write
Must set to L during the byte write
Must set to L during the byte write
Must set to L during the byte write
Must set to L during the byte write
Must set to L during the byte write
(H = Enable, L = Disable)
PIN AFFECTED
(WRITE OPERATION)
SOURCE PIN
(READ OPERATION)
CPU, CPU
Register value
–
Register value
–
Register value
–
Register value
–
Register value
–
Register value
–
Register value
–
Register value
Single-pulse initialization
1. Device is in normal operating mode (frequencies selected by FS[4:0] as usual).
2. Put device into SMBus mode (set write enable bit according to specification).
3. Put device into required operating mode via the SMBus.
4. Set Byte8/Bit6 to H. Byte8 is a TI control byte, Bit6 is the ARM bit.
a. The device continues running as in the normal operating mode, but the CPUx/CPUx outputs are pulled
to low/high, respectively; i.e., the clock is low.
b. All other clocks (PCI, LDT66, USB, 48-MHz, REFCLOCK) continue running as long as they are not
disabled by the SMBus or other means.
5. Set Byte8/Bit7 to H. Byte8/Bit 7 is the SHOOT bit.
a. The device recognizes a rising edge on this bit and sends a single high pulse on CPUx. The CPUx
output is complementary (low). The pulse duration depends on frequency settings for the CPU-BUS
(half of the period).
b. CPU1 or CPU0 can still be enabled/disabled via the SMBus as usual.
6. Set Byte8/Bit7 back to L for the next shot.
a. Because the device only detects L!H transitions, this bit must be reset to L.
7. Now the device is ready for the next pulse (write H to Byte8/Bit7).
8. When setting the ARM bit to L, the single-shot feature is disabled and the device runs as usual.
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