CDC960 Datasheet, PDF (26/38 Pages) Texas Instruments – 200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE

CDC960
200ĆMHz CLOCK SYNTHESIZER/DRIVER
WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE
SCAS675 – APRIL 2002
PCI, LDT (33 MHz), PCI_F and LDT (66 MHz), C_L = 30 pF, R_L = 500 Ω (continued)
PARAMETER
FROM
TO
(INPUT) (OUTPUT)
TEST CONDITIONS
MIN TYP^† MAX Unit
tsk(ow)
↑ edges to LDT time
independent (3.3 V)
↑ edges to LDT time variant
skew
↑ edges to LDT time
independent (3.3)
↑ edges to LDT time variant
skew
PCIx
PCIx
PCIx
PCIx
LDTx
LDTx
f(PCI/LDT) = 33.3 MHz
LDTx
LDTx
f(PCI/LDT)= 33.3 MHz/66.7 MHz
500
200
ps
500
200
PCI pulse skew
PCIn
PCIn f(PCI) = 33.3 MHz
1.5
tsk(p)
LDT pulse skew
LDTn
LDTn f(LDT) = 66.7 MHz
1.4
tw(H)
Pulse duration, high PCI (33 MHz)
Pulse duration, high LDT (66 MHz)
f(PCI) = 33.3 MHz
13.6
f(LDT) = 66.7 MHz
6.2
tw(L)
Pulse duration, low PCI (33 MHz)
Pulse duration, low LDT (66 MHz)
f(PCI) = 33.3 MHz
16.0
f(LDT) = 66.7 MHz
8.4
tr
Rise time PCI/LDT (33 MHz), LDT (66 MHz)
Vref = 20% to 80% of VO
0.7
2.9
3.7
ns
3.6
ns
ns
1.6 ns
1.2 V/ns
tf
Fall time PCI/LDT (33 MHz), LDT (66 MHz)
Vref = 20% to 80% of VO
0.6
3.5
1.6 ns
1.2 V/ns
vr
0.3
vf
Edge rate rising edge (maintained during total transition) Vref = 20% to 60% of VDD
0.4
† _{All typical values are measured at their nominal VDD values.}
1.7
V/ns
1.7
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