CDC960 Datasheet, PDF (21/38 Pages) Texas Instruments – 200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE

CDC960
200ĆMHz CLOCK SYNTHESIZER/DRIVER
WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE
SCAS675 – APRIL 2002
switching characteristics, V_DD = MIN to MAX, T_A = 0°C to 70°C
PARAMETER
TEST CONDITIONS
MIN TYP^† MAX UNIT
v(over)/v(under) Overshoot/undershoot
All clocks
tsu(disable)
PCI_Stop↓ or LDT_Stop↓ to PCI_F↑
f(PCI/LDT) = 33/66 MHz to disable
PCI/LDT in next cycle (PCI/LDT = low)
10
±0.7
ns
th(disable)
PCI_Stop↓ or LDT_Stop↓ to PCI_F↑
f(PCI/LDT) = 33/66 MHz to disable
PCI/LDT in next cycle (PCI/LDT = low)
0
ns
tsu(enable)
PCI_Stop↑ or LDT_Stop↑ to PCI_F↑
f(PCI/LDT) = 33/66 MHz to enable PCI/LDT
in next cycle (PCI/LDT = high)
10
ns
th(enable)
PCI_Stop↑ or LDT_Stop↑ to PCI_F↑
f(PCI/LDT) = 33/66 MHz to enable PCI/LDT
in next cycle (PCI/LDT = high)
0
ns
SSC(midx)
SSC spread amount
f(CPU) = 100 MHz to 200 MHz
–0.5
%
f(mod)
SSC modulation frequency
f(CPU) = 100 MHz to 200 MHz
31.4
kHz
tstab
Stabilization time^†
FS0, FS1, FS2 or SMBus update
After power up
0.03
3
ms
0.13
3
† _{Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for}
phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at XIN. Until phase lock is obtained, the specifications
for propagation delay and skew parameters given in the switching characteristics tables are not applicable. Stabilization time is defined as the
time from when VDD achieves its nominal operating level until the output frequency is stable and operating within specification.
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