CDC960 Datasheet, PDF (2/38 Pages) Texas Instruments – 200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE

CDC960
200ĆMHz CLOCK SYNTHESIZER/DRIVER
WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE
SCAS675 – APRIL 2002
description (continued)
The CPU bus is a 3.3-V differential push-pull output type. All others are single-ended CMOS buffers.
The host frequencies are fixed and are controlled by the FS0, FS1 and FS2 signals at power-up. The CPU bus
frequencies are 200, 166, 133 and 100 MHz.
Because the CDC960 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
With use of external reference clock, this signal must be fixed-frequency and fixed-phase prior stabilization time
starts.
FUNCTION TABLES
SMBUS
CONTROLLED
INPUTS
DEVICE FREQUENCY SELECT FUNCTIONS
OUTPUTS
L
L
H
H
H H H 200 MHz 33 MHz
33 MHz
48 MHz 24 MHz 14.31818 MHz
L
L
H
L
H H H 200 MHz 33 MHz
66 MHz
48 MHz 24 MHz 14.31818 MHz
L
L
L
H
H H H 200 MHz 33 MHz
33 MHz
48 MHz 48 MHz 14.31818 MHz
L
L
L
L
H H H 200 MHz 33 MHz
66 MHz
48 MHz 48 MHz 14.31818 MHz
L
L
H/L H/L H H L 166 MHz 33 MHz 33/66 MHz 48 MHz 24/48 MHz 14.31818 MHz
L
L
H/L H/L H L H 133 MHz 33 MHz 33/66 MHz 48 MHz 24/48 MHz 14.31818 MHz
L
L
H/L H/L H L L 100 MHz 33 MHz 33/66 MHz 48 MHz 24/48 MHz 14.31818 MHz
L
L
X
H
L LH
Xin
Xin/6
Xin/6
L
L
L
L
X
L
L LH
Xin
Xin/6
Xin/3
L
L
L
f(xin) = 0 to
L
200 MHz
L
L
H
H
L HH
Xin
Xin/6
Xin/6
Xin/2
Xin/4
Xin
L
L
H
L
L HH
Xin
Xin/6
L
L
L
H
L HH
Xin
Xin/6
Xin/3
Xin/6
Xin/2
Xin/2
Xin/4
Xin/2
Xin
f(xin) = 0 to
Xin
16 MHz
L
L
L
L
L HH
Xin
Xin/6
Xin/3
Xin/2
Xin/2
Xin
L
L
X
X
L HL
Reserved for future use
L
L
X
X
L LL
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
L
H
H/L H/L H H H 90 MHz 30 MHz 30/60 MHz 48 MHz 24/48 MHz 14.31818 MHz
–10%
L
H
H/L H/L H H L 119 MHz 30 MHz 30/60 MHz 48 MHz 24/48 MHz 14.31818 MHz
–10%
L
H
H/L H/L H L H 180 MHz 36.3 MHz 36.3/72.6 MHz 48 MHz 24/48 MHz 14.31818 MHz
–10%
L
H
H/L H/L H L L 180 MHz 30 MHz 30/60 MHz 48 MHz 24/48 MHz 14.31818 MHz
–10%
L
H
H/L H/L L H H 111 MHz 36.9 MHz 36.9/73.9 MHz 48 MHz 24/48 MHz 14.31818 MHz
10%
L
H
H/L H/L L H L 148 MHz 36.9 MHz 36.9/73.9 MHz 48 MHz 24/48 MHz 14.31818 MHz
10%
L
H
H/L H/L L L H 222 MHz 44.4 MHz 44.4/88.8 MHz 48 MHz 24/48 MHz 14.31818 MHz
10%
L
H
H/L H/L L L L 222 MHz 36.9 MHz 36.9/73.9 MHz 48 MHz 24/48 MHz 14.31818 MHz
10%
H
X
H/L H/L X X X
Not-yet-defined settings
† _{If the REF, USB, and FDC outputs are disabled in by pass mode, the Xin-input can be driven with an external clock signal from 0 MHz to 200 MHz.}
Otherwise the maximum input frequency is limited to 16 MHz.
‡ _{24/48_SEL and PCI/LDT_SEL inputs operate independently from each other and the frequency of the corresponding bus, as shown in detail}
for the 200-MHz configuration.
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