CDC960 Datasheet, PDF (6/38 Pages) Texas Instruments – 200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE

CDC960
200ĆMHz CLOCK SYNTHESIZER/DRIVER
WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE
SCAS675 – APRIL 2002
Terminal Functions (Continued)
TERMINAL
NAME
NO.
VDDA
43
VDDF
32
XIN
3
XOUT
4
24/48_SEL & FDC
28
I/O
DESCRIPTION
P Analog VDD: Connected to 3.3-V power supply through filter. Used to supply the main CPU-PLL
on the chip
P Analog VDD for 48-MHz PLL: Connected to 3.3-V power supply through filter. Used to supply the
48-MHz PLL on the chip
I Crystal input – 14.318 MHz
Crystal Connection or External Reference: Reference crystal input or external reference clock
input. This pin includes an internal 36-pF load capacitance to eliminate the need for an external
load capacitor.
O Crystal output – 14.318 MHz
Crystal Connection: Reference crystal feedback. This output includes an internal 36-pF load
capacitance to eliminate the need for an external load capacitor.
I/O 3.3-V super I/O clock output: The super I/O clock can be strapped for 24 MHz or 48 MHz. This
input has a 150-kΩ internal pullup resistor.
Low = 48-MHz output, High = 24-MHz output
connecting SCLK and SDATA to 5-V SMBus signals
SCLK and SDATA of CDC960 have been designed to work within a 3.3-V supply voltage environment only. In
order to connect SCLK and SDATA to a 5-V SMBus configuration, external circuitry is required. A simple and
inexpensive solution is to use clamping diodes. Two approaches are recommended for this solution:
1. Using Zener diode to clamp to GND in reverse-biased direction
3.3 V
SCLK
OR
VO
SDATA
Driver
R1
D1
150 kΩ
VIO
SCLK
or
SDATA
CDC960
Figure 1. SCLK SDATA Connection to 5-V SMBus Using Zener Diode
Zener diode D1 in Figure 1 is chosen such that the Zener voltage (V_ZK) cannot exceed 300 mV above V_DD of
the CDC960. The minimum value of V_ZK must be greater than 2.1 V to meet minimum requirement for V_IH of
the CDC960. The value of R1 is chosen to satisfy requirements both for I_OH of the driver of SCLK and SDATA
and for V_OL and I_OL of SDATA of CDC960.
ǒ Ǔ ^{IOH v}
VO * VIO
R1 ) RS
(For the driver of SCLK and SDATA. R_S is the source driver impedance.)
(1)
2
mA
v
0.8 V
R1 ) ZO
v
6
mA
(For a SDATA of CDC960, 25 W t ZO t 47 W)
(2)
ǒ Ǔ _{R1 ) ZO 1.75 mA t 0.4 V (For a SDATA of CDC960, 25 W t ZO t 47 W)}
(3)
6
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