SI5344H-42H Datasheet, PDF (9/56 Pages) Silicon Laboratories – HIGH-FREQUENCY,

Si5344H/42H
Table 5. Differential Clock Output Specifications (Continued)
(V_DD = 1.8 V ±5%, V_DDA = 3.3V ±5%, V_DDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Output Voltage Swing¹ F_out>1.5 GHz
V_OUT
Differential High-Speed Output
Mode (AC-Coupled)
Min
Typ
Max
Unit
380 650 @ 1.7 GHz 800 mVpp_se
600 @ 2.1 GHz
580 @ 2.5 GHz
500@ 2.75 GHz
F_out<1.5 GHz
Common Mode
Voltage^1,4
(100 Ω load line-to-
line)
V_OUT
V_CM
LVDS
LVPECL¹
0.001 MHz <F_out<717.5 MHz
LVPECL
717.5 MHz < F_out < 1500 MHz
V_DDO = 3.3 V
LVDS
LVPECL
V_DDO = 2.5 V
LVPECL
LVDS
400
640
680
1.10
1.90
1.10
450
750
750
1.20
2.00
1.20
500 mVpp_se
900
830
1.30
V
2.10
V
1.30
V
V_DDO = 1.8 V
Sub-LVDS 0.80
0.90
1.0
V
Rise and Fall Times
t_R/t_F Differential High-Speed Output
—
70
110
ps
(20% to 80%)
Mode (AC-Coupled)
F_out>1.5 GHz
Normal Mode
F_out<1.5 GHz
—
90
120
Note:
1. For normal mode, the amplitude and common-mode settings are programmable through register settings and can be stored in
NVM. Each output driver can be programmed independently. The typical LVDS maximum is 100 mV (or 80 mV) higher than
the TIA/EIA-644 maximum. When in LVPECL mode and f_OUT>717.5 MHz note V_OUT may not meet standard LVPECL levels,
but provides the greatest output voltage swing. Also note that the output voltage swing specifications are given in peak-to-
peak single-ended swing.
2. Max frequency using MultiSynth outputs is determined by the VCO frequency. Please use ClockBuilder Pro to determine the
maximum output frequency for any given frequency plan.
3. High-speed outputs indicates no multiSynth is used (i.e., not fractional synthesis).
OUTx
Vcm
Vcm
Vpp_se
Vpp_se
Vpp_diff = 2*Vpp_se
OUTx
4. Not all combinations of voltage swing and common mode voltages settings are possible. See the reference manual for details.
5. Measured for 156.25 MHz carrier frequency. 100 mVpp sinewave noise added to VDDO = 3.3 V and noise spur amplitude
measured.
6. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at
156.25 MHz. Refer to “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems” for
guidance on crosstalk optimization. Note that all active outputs must be terminated when measuring crosstalk.
Rev. 1.0
9