SI5344H-42H Datasheet, PDF (38/56 Pages) Silicon Laboratories – HIGH-FREQUENCY,

Si5344H/42H
4.8.8. Output Enable/Disable
The OE pin provides a convenient method of disabling or enabling the output drivers. When the OE pin is held high
all outputs will be disabled. When held low, the outputs will be enabled. Outputs in the enabled state can be
individually disabled through register control.
4.8.9. Output Driver State When Disabled
The disabled state of an output driver is configurable as: disable low, disable high, or disable high-impedance.
4.8.10. Synchronous Output Disable Feature
The output drivers provide a selectable synchronous disable feature. Output drivers with this feature turned on will
wait until a clock period has completed before the driver is disabled. This prevents unwanted runt pulses from
occurring when disabling an output. When this feature is turned off, the output clock will disable immediately
without waiting for the period to complete.
4.8.11. Output Skew Control (t₀ – t₃)
The Si5344H/42H uses independent MultiSynth dividers (N₀ - N₃) to generate up to 4 unique frequencies to its 10
outputs through a crosspoint switch. By default all clocks are phase aligned. A delay path (t₀ - t₃) associated with
each of these dividers is available for applications that need a specific output skew configuration. This is useful for
PCB trace length mismatch compensation. The resolution of the phase adjustment is approximately 0.28 ps per
step definable in a range of ±9.14 ns. Phase adjustments are register configurable. An example of generating two
frequencies with unique configurable path delays is shown in Figure 23.
÷N₀
t₀
÷N₁
t₁
÷N₂
t₂
÷N₃
t₃
VDDO0
÷R₀
OUT0
OUT0
VDDO1
÷R₁
OUT1
OUT1
VDDO2
÷R₂
OUT2
OUT2
VDDO3
÷R₃
OUT3
OUT3
Figure 23. Example of Independently Configurable Path Delays
All phase delay values are restored to their default values after power-up, hard reset, or a reset using the RST pin.
Phase delay default values can be written to NVM allowing a custom phase offset configuration at power-up or
after power-on reset, or after a hardware reset using the RST pin.
4.8.12. Output Divider (R) Synchronization
All the output R dividers are reset to a known state during the power-up initialization period. This ensures
consistent and repeatable phase alignment across all output drivers. Resetting the device using the RST pin or
asserting the hard reset bit will have the same result. Asserting the sync register bit provides another method of re-
aligning the R dividers without resetting the device.
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