SI5344H-42H Datasheet, PDF (28/56 Pages) Silicon Laboratories – HIGH-FREQUENCY,

Si5344H/42H
48-54MHz
XO
48-54MHz
XO
48-54MHz
XTAL
XA
XB
2xC_L
OSC
2xCL
÷P_REF
100
XA
XB
2xC_L
OSC
2xC_L
÷P_REF
XA
XB
2xC_L
OSC
2xCL
÷P_REF
Crystal Resonator
Connection
Differential XO
Connection
Single-ended XO
Connection
Figure 11. Crystal Resonator and External Reference Clock Connection Options
4.6. Inputs (IN0, IN1)
There are two inputs that can be used to synchronize the DSPLL. The inputs accept both differential and single-
ended clocks. Input selection can be manual (pin or register controlled) or automatic with user definable priorities.
4.6.1. Manual Input Switching (IN0, IN1)
Input clock selection can be made manually using the IN_SEL pin or through a register. A register bit determines
input selection as pin selectable or register selectable. The IN_SEL pin are selected by default. If there is no clock
signal on the selected input, the device will automatically enter free-run or holdover mode.
Table 15. Manual Input Selection Using IN_SEL Pin
IN_SEL
0
1
Selected Input
IN0
IN1
28
Rev. 1.0