SI5344H-42H Datasheet, PDF (29/56 Pages) Silicon Laboratories – HIGH-FREQUENCY,

Si5344H/42H
4.6.2. Automatic Input Selection (IN0, IN1)
An automatic input selection state machine is available in addition to the manual switching option. In automatic
mode, the selection criteria is based on input clock qualification, input priority, and the revertive option. Only input
clocks that are valid can be selected by the automatic clock selection state machine. If there are no valid input
clocks available the DSPLL will enter the holdover mode. With revertive switching enabled, the highest priority
input with a valid input clock is always selected. If an input with a higher priority becomes valid then an automatic
switchover to that input will be initiated. With non-revertive switching, the active input will always remain selected
while it is valid. If it becomes invalid an automatic switchover to a valid input with the highest priority will be
initiated.
4.6.3. Hitless Input Switching
Hitless switching is a feature that prevents a phase transient from propagating to the output when switching
between two clock inputs that have a fixed phase relationship. A hitless switch can only occur when the two input
frequencies are frequency locked meaning that they have to be exactly at the same frequency, or at a fractional
frequency relationship to each other. When hitless switching is enabled, the DSPLL simply absorbs the phase
difference between the two input clocks during a input switch. When disabled, the phase difference between the
two inputs is propagated to the output at a rate determined by the DSPLL Loop Bandwidth. The hitless switching
feature supports clock frequencies down to the minimum input frequency of 8 kHz.
4.6.4. Glitchless Input Switching
The DSPLL has the ability of switching between two input clock frequencies that are up to ±500 ppm apart. The
DSPLL will pull-in to the new frequency using the DSPLL Loop Bandwidth or using the Fastlock Loop Bandwidth if
enabled. The loss of lock (LOL) indicator will assert while the DSPLL is pulling-in to the new clock frequency. There
will be no output runt pulses generated at the output during the transition.
4.6.5. Input Configuration and Terminations
Each of the inputs can be configured as differential or single-ended LVCMOS. The recommended input termination
schemes are shown in Figure 12. Differential signals must be ac-coupled, while single-ended LVCMOS signals can
be ac or dc-coupled. Unused inputs can be disabled and left unconnected when not in use.
Rev. 1.0
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