SI5344H-42H Datasheet, PDF (10/56 Pages) Silicon Laboratories – HIGH-FREQUENCY,

Si5344H/42H
Table 5. Differential Clock Output Specifications (Continued)
(V_DD = 1.8 V ±5%, V_DDA = 3.3V ±5%, V_DDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Differential Output
Impedance⁴
Z_O
—
Power Supply Noise PSRR
10 kHz sinusoidal noise
—
Rejection⁵
100 kHz sinusoidal noise
—
500 kHz sinusoidal noise
—
1 MHz sinusoidal noise
—
Output-output Cross- XTALK Measured spur from adjacent
—
talk
output⁶
Typ
100
–101
–96
–99
–97
–88
Max
Unit
—

—
dBc
—
—
—
—
dBc
Note:
1. For normal mode, the amplitude and common-mode settings are programmable through register settings and can be stored in
NVM. Each output driver can be programmed independently. The typical LVDS maximum is 100 mV (or 80 mV) higher than
the TIA/EIA-644 maximum. When in LVPECL mode and f_OUT>717.5 MHz note V_OUT may not meet standard LVPECL levels,
but provides the greatest output voltage swing. Also note that the output voltage swing specifications are given in peak-to-
peak single-ended swing.
2. Max frequency using MultiSynth outputs is determined by the VCO frequency. Please use ClockBuilder Pro to determine the
maximum output frequency for any given frequency plan.
3. High-speed outputs indicates no multiSynth is used (i.e., not fractional synthesis).
OUTx
OUTx
Vcm
Vcm
Vpp_se
Vpp_se
Vpp_diff = 2*Vpp_se
4. Not all combinations of voltage swing and common mode voltages settings are possible. See the reference manual for details.
5. Measured for 156.25 MHz carrier frequency. 100 mVpp sinewave noise added to VDDO = 3.3 V and noise spur amplitude
measured.
6. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at
156.25 MHz. Refer to “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems” for
guidance on crosstalk optimization. Note that all active outputs must be terminated when measuring crosstalk.
10
Rev. 1.0