SI5344H-42H Datasheet, PDF (6/56 Pages) Silicon Laboratories – HIGH-FREQUENCY,

Si5344H/42H
Table 3. Input Specifications
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max
Unit
Standard Differential or Single-Ended - AC Coupled (IN0/IN0, IN1/IN1)
Input Frequency Range
f_{IN_DIFF}
Differential
0.008 — 750
MHz
Single-ended/LVCMOS 0.008 — 250
MHz
Voltage Swing¹
V_IN
Differential AC Coupled 100 — 1800 mVpp_se
f_in < 250 MHz
Slew Rate^{2, 3}
Differential AC Coupled 225
250 MHz < f_in < 750 MHz
Single-Ended AC Coupled⁵ 100
f_in < 250 MHz
— 1800 mVpp_se
— 3600 mVpp_se
SR
400 —
—
V/µs
Duty Cycle
DC
40
—
60
%
Capacitance
C_IN
— 0.3 —
pF
Pulsed CMOS - DC Coupled (IN0, IN1)
Input Frequency
Input Voltage⁴
f_{IN_PULSED_CMOS4}
V_IL
V_IH
Slew Rate^{2, 3}
SR
0.008 — 250
–0.2 — 0.4
0.8
—
—
400 —
—
MHz
V
V
V/µs
Duty Cycle
DC
40
—
60
%
Minimum Pulse Width
PW
Pulse Input
1.6
—
—
ns
Input Resistance
R_IN
—
8
—
k
REFCLK (applied to XA/XB)
Notes:
1. Voltage swing is specified as single-ended mVpp.
OUTx
OUTx
Vcm
Vcm
Vpp_se
Vpp_se
Vpp_diff = 2*Vpp_se
2. Imposed for jitter performance.
3. Rise and fall times can be estimated using the following simplified equation: tr/tf_80-20 = ((0.8 – 0.2) x V_{IN_Vpp_se}) / SR
4. This mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz that must be dc-coupled because they
have a duty cycle significantly less than 50%. A typical application example is a low-frequency video frame sync pulse.
Since the input thresholds (V_IL, V_IH) of this buffer are non-standard (0.4 V and 0.8 V, respectively) refer to the input
attenuator circuit for dc-coupled pulsed LVCMOS in the Family Reference Manual. Otherwise, for standard LVCMOS
input clocks, use the Standard Differential or Single-Ended ac-coupled input mode.
5. Refer to the Family Reference Manual if you're using a single-ended AC coupled inputs with voltage swing exceeding
3.4 V.
6
Rev. 1.0