SI5344H-42H Datasheet, PDF (15/56 Pages) Silicon Laboratories – HIGH-FREQUENCY,

Si5344H/42H
Table 8. Performance Characteristics (Continued)
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
RMS Phase Jitter⁴
Symbol
J_GEN
Test Condition
Integer High-Speed Mode
1 MHz to 40 MHz
Integer High-Speed Mode
12 kHz to 20 MHz
Fractional MultiSynth Mode
12 kHz to 20 MHz
Min Typ Max Unit
— 0.050 — ps RMS
— 0.085 0.140 ps RMS
— 0.120 0.160 ps RMS
Notes:
1. Actual loop bandwidth might be lower; please refer to CBPro for actual value for your frequency plan.
2. Lock Time can vary significantly depending on several parameters, such as bandwidths, LOL thresholds, etc. For this
case, lock time was measured with nominal and fastlock bandwidths set to 100 Hz, LOL set/clear thresholds of 6/0.6
ppm respectively, using IN0 as clock reference by removing the reference and enabling it again, then measuring the
delta time between the first rising edge of the clock reference and the LOL indicator de-assertion.
3. Measured as time from valid VDD/VDDA rails (90% of their value) to when the serial interface is ready to respond to
commands.
4. Jitter generation test conditions:
Integer High-Speed Mode: f_IN = 19.44 MHz, f_OUT = 2.104658 GHz diff. high-speed output, loop bandwidth = 100 Hz.
Fractional MultiSynth (normal) Mode: f_IN = 19.44 MHz, f_OUT = 156.25 MHz LVPECL, loop bandwidth = 100 Hz.
Rev. 1.0
15