SI5344H-42H Datasheet, PDF (12/56 Pages) Silicon Laboratories – HIGH-FREQUENCY,

Si5344H/42H
Table 6. LVCMOS Clock Output Specifications (Continued)
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, V_DDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Output Voltage Low^1,
2, 3
V_OL
OUTx_CMOS_DRV=1
OUTx_CMOS_DRV=2
V_DDO = 3.3 V
I_OL = 10 mA —
I_OL = 12 mA —
— V_DDO V
— ^{x 0.15}
OUTx_CMOS_DRV=3
I_OL = 17 mA —
—
V_DDO = 2.5 V
OUTx_CMOS_DRV=1
OUTx_CMOS_DRV=2
I_OL = 6 mA
—
— V_DDO V
I_OL = 8 mA
—
— ^{x 0.15}
OUTx_CMOS_DRV=3
I_OL = 11 mA —
—
V_DDO = 1.8 V
OUTx_CMOS_DRV=2
OUTx_CMOS_DRV=3
I_OL = 4 mA
—
— V_DDO V
I_OL = 5 mA
—
— ^{x 0.15}
LVCMOS Rise and
Fall Times³
(20% to 80%)
tr/tf f_OUT = 156.25 MHz
CMOS_DRV = 3
VDDO = 3.3 V
VDDO = 2.5 V
VDDO = 1.8 V
— 400 600 ps
— 450 600 ps
— 550 750 ps
Notes:
1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3.
Refer to the Family Reference Manual or contact Silicon Labs for more details on register settings.
2. I_OL/I_OH is measured at V_OL/V_OH as shown in the dc test configuration.
3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50  PCB trace. A 5 pF
capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.
IOL/IOH
IDDO
Zs
VOL/VOH
OUT
OUT
AC Test Configuration
Trace length 5 inches
50 
499 
4.7 pF
DC Block
50 probe, scope
56 
50 
499 
4.7 pF
DC Block
50 probe, scope
56 
12
Rev. 1.0