SI5344H-42H Datasheet, PDF (26/56 Pages) Silicon Laboratories – HIGH-FREQUENCY,

Si5344H/42H
Power-Up
Reset and
Initialization
No valid
input clocks
selected
An input is qualified
and available for
selection
Free-run
Valid input clock
selected
Lock Acquisition
(Fast Lock)
No
Yes
Is holdover
history valid?
Holdover
Mode
Selected input
clock fails
Locked
Mode
Phase lock on
selected input
clock is achieved
Figure 9. Modes of Operation
4.3.2. Freerun Mode
The DSPLL will automatically enter freerun mode once power is applied to the device and initialization is complete.
The frequency accuracy of the generated output clocks in freerun mode is entirely dependent on the frequency
accuracy of the external crystal or reference clock on the XA/XB pins. For example, if the crystal frequency is
±100 ppm, then all the output clocks will be generated at their configured frequency ±100 ppm in freerun mode.
Any drift of the crystal frequency will be tracked at the output clock frequencies. A TCXO or OCXO is
recommended for applications that need better frequency accuracy and stability while in freerun or holdover
modes.
4.3.3. Lock Acquisition Mode
The device monitors all inputs for a valid clock. If at least one valid clock is available for synchronization, the
DSPLL will automatically start the lock acquisition process. If the fast lock feature is enabled, the DSPLL will
acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting
when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO
frequency change as it pulls-in to the input clock frequency.
4.3.4. Locked Mode
Once locked, the DSPLL will generate output clocks that are both frequency and phase locked to their selected
input clocks. At this point any XTAL frequency drift will not affect the output frequency. A loss of lock pin (LOL) and
status bit indicate when lock is achieved. See section 4.7.4 for more details on the operation of the loss of lock
circuit.
4.3.5. Holdover Mode
The DSPLL will automatically enter holdover mode when the selected input clock becomes invalid and no other
valid input clocks are available for selection. The DSPLL uses an averaged input clock frequency as its final
holdover frequency to minimize the disturbance of the output clock phase and frequency when an input clock
suddenly fails. The holdover circuit for the DSPLL stores up to 120 seconds of historical frequency data while
locked to a valid clock input. The final averaged holdover frequency value is calculated from a programmable
window within the stored historical frequency data. Both the window size and the delay are programmable as
shown in Figure 10. The window size determines the amount of holdover frequency averaging. The delay value
allows ignoring frequency data that may be corrupt just before the input clock failure.
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Rev. 1.0