SI5344H-42H Datasheet, PDF (34/56 Pages) Silicon Laboratories – HIGH-FREQUENCY,

Si5344H/42H
The LOL frequency monitors have an adjustable sensitivity which is register configurable from 0.2 ppm to
20000 ppm. Having two separate frequency monitors allows for hysteresis to help prevent chattering of LOL status.
An example configuration where LOCK is indicated when there is less than 0.2 ppm frequency difference at the
inputs of the phase detector and LOL is indicated when there’s more than 2 ppm frequency difference is shown in
Figure 19.
LOL
LOCKED
Clear LOL
Threshold
Set LOL
Threshold
Lock Acquisition
Hysteresis
Lost Lock
0
0.2
2
20,000
Phase Detector Frequency Difference (ppm)
Figure 19. LOL Set and Clear Thresholds
Note: In this document, the terms, LVDS and LVPECL, refer to driver formats that are compatible with these signaling
standards.
An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to
completely lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering
as the DSPLL completes lock acquisition. The configurable delay value depends on frequency configuration and
loop bandwidth of the DSPLL and is automatically calculated using the ClockBuilder Pro utility.
4.7.5. Interrupt pin (INTR)
An interrupt pin (INTR) indicates a change in state of the status indicators (LOS, OOF, LOL, HOLD). Any of the
status indicators are maskable to prevent assertion of the interrupt pin. The state of the INTR pin is reset by
clearing the status register that caused the interrupt.
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