SI5344H-42H Datasheet, PDF (44/56 Pages) Silicon Laboratories – HIGH-FREQUENCY,

Si5344H/42H
Table 19. Pin Descriptions Table
Pin Name
Inputs
XA
XB
X1
X2
IN0
IN0
IN1
IN1
Si5342H Si5344H
Pin
Pin _{Pin Type}¹
Number Number
Function
5
5
6
6
4
4
7
7
43
43
44
44
1
1
2
2
I
Crystal Input
I
Input pins for external crystal (XTAL). Alternatively these
pins can be driven with an external reference clock (REF-
CLK). An internal register bit selects XTAL or REFCLK
mode. Default is XTAL mode.
I
XTAL Shield
I
Connect these pins directly to the XTAL ground pins. X1,
X2 and the XTAL ground pins should be separated from
the PCB ground plane. Contact Silicon Labs for layout
guidelines. These pins should be left disconnected when
connecting XA/XB pins to an external reference clock
(REFCLK).
I
Clock Inputs
I
These pins accept an input clock for synchronizing the
device. They support both differential and single-ended
I
clock signals. Refer to "4.6.5. Input Configuration and Ter-
minations" on page 29 for input termination options.
I
These pins are high-impedance and must be terminated
externally. The negative side of the differential input must
be grounded through a capacitor when accepting a sin-
gle-ended clock.
Outputs
OUT0
20
20
OUT0
19
19
OUT1
25
25
OUT1
24
24
OUT2
—
31
OUT2
—
30
OUT3
—
36
OUT3
—
35
O
Output Clocks
O
These output clocks support a programmable signal
swing and common mode voltage. Desired output signal
O
format is configurable using register control. Termination
recommendations are provided in “4.8.3. Differential Out-
O
put Terminations” . Unused outputs should be left uncon-
O
nected.
O
O
O
Notes:
1. I = Input, O = Output, P = Power
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation. These pins are push-pull outputs and do
not require an external pull-up resistor.
44
Rev. 1.0