SI5344H-42H Datasheet, PDF (46/56 Pages) Silicon Laboratories – HIGH-FREQUENCY,

Si5344H/42H
Table 19. Pin Descriptions Table
Pin Name
Si5342H Si5344H
Pin
Pin _{Pin Type}¹
Number Number
Function
Control/Status
INTR
33
33
RST
17
17
OE
12
12
LOL
27
27
LOS0
30
—
LOS1
31
—
LOS_XAXB 28
28
IN_SEL
3
3
RSVD_GND 37
O
Interrupt
This pin is asserted low when a change in device status
has occurred. This pin must be pulled-up using an exter-
nal resistor of at least 1 k. It should be left unconnected
when not in use. See Note ².
I
Device Reset
Active low input that performs power-on reset (POR) of
the device. Resets all internal logic to a known state and
forces the device registers to their default values. Clock
outputs are disabled during reset. This pin is internally
pulled-up and can be left unconnected when not in use.
See Note ².
I
Output Enable
This pin disables all outputs when held high. This pin is
internally pulled low and can be left unconnected when
not in use. See Note ².
O
Loss Of Lock
This output pin indicates when the DSPLL is locked (high)
or out-of-lock (low). It can be left unconnected when not in
use. See Note ³.
O
Loss Of Signal for IN0 (Si5342H only)
This pin indicate a loss of clock at the IN0 pin when low.
See Note ³.
O
Loss Of Signal for IN1 (Si5342H only)
This pin indicate a loss of clock at the IN1 pin when low.
See Note ³.
O
Loss Of Signal on XA/XB Pins
This pin indicates a loss of signal at the XA/XB pins when
low. See Note ³.
I
Input Reference Select
The IN_SEL pin is used in manual pin controlled mode to
select the active clock input as shown in Table 15 on
page 28. These pins are internally pulled low. See Note ².
—
Reserved - Connect to Ground
This pin is connected to the die and must be connected to
ground.
Notes:
1. I = Input, O = Output, P = Power
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation. These pins are push-pull outputs and do
not require an external pull-up resistor.
46
Rev. 1.0