SI5344H-42H Datasheet, PDF (14/56 Pages) Silicon Laboratories – HIGH-FREQUENCY,

Si5344H/42H
Table 8. Performance Characteristics
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
PLL Loop Bandwidth Pro-
gramming Range¹
f_BW
0.1 — 4000 Hz
Initial Start-Up Time
t_START Time from power-up to when the
—
30
45
ms
device generates free-running clocks
PLL Lock Time²
t_ACQ
f_IN = 19.44 MHz
— 280 300
ms
Output Delay Adjustment t_{DELAY_frac}
f_VCO = 14 GHz
— 0.28 —
ps
t_{DELAY_int}
— 71.4 —
ps
t_RANGE
— ±9.14 —
ns
POR to Serial Interface
Ready³
t_RDY
—
—
15
ms
Jitter Peaking
J_PK
Measured with a frequency plan run- —
—
0.1
dB
ning a 25 MHz input, 25 MHz output,
and a Loop Bandwidth of 4 Hz
Jitter Tolerance
J_TOL
Compliant with G.8262 Options 1 and —
2 Carrier Frequency = 2.103125 GHz
Jitter Modulation
Frequency = 10 Hz
3180
— UI pk-pk
Maximum Phase Tran-
t_SWITCH
Only valid for a single automatic
—
—
2.0
ns
sient During a Hitless
switch between two input clocks run-
Switch
ning at the same frequency
Only valid for a single manual switch
1.3
between two input clocks running at
the same frequency
Pull-in Range
Input-to-Output Delay
Variation
_P
—
t_IODELAY Measured between a common 2 MHz —
input and 2 MHz output with different
MultiSynths on the same part.
DSPLL bandwidth = 4 kHz.
500 —
—
1.8
ppm
ns
Measured between a common 2 MHz —
—
2.0
ns
input and 2 MHz output with different
MultiSynths between different parts.
DSPLL bandwidth = 4 kHz.
14
Rev. 1.0