SI5344H-42H Datasheet, PDF (16/56 Pages) Silicon Laboratories – HIGH-FREQUENCY,

Si5344H/42H
Table 9. I²C Timing Specifications (SCL,SDA)
Parameter
Symbol Test Condition
SCL Clock Frequency
f_SCL
SMBus Timeout
—
Hold time (repeated)
START condition
Low period of the SCL
clock
HIGH period of the SCL
clock
Set-up time for a
repeated START condi-
tion
Data hold time
Data set-up time
Rise time of both SDA
and SCL signals
Fall time of both SDA
and SCL signals
Set-up time for STOP
condition
Bus free time between a
STOP and START con-
dition
Data valid time
Data valid acknowledge
time
t_HD:STA
t_LOW
t_HIGH
t_SU:STA
t_HD:DAT
t_SU:DAT
t_r
t_f
t_SU:STO
t_BUF
t_VD:DAT
t_VD:ACK
When Timeout is
Enabled
Min
Max
Standard Mode
100 kbps
—
100
25
35
4.0
—
4.7
—
4.0
—
4.7
—
100
—
250
—
—
1000
—
300
4.0
—
4.7
—
—
3.45
—
3.45
Min
Max
Fast Mode
400 kbps
—
400
25
35
0.6
—
1.3
—
0.6
—
0.6
—
100
—
100
—
20
300
—
300
0.6
—
1.3
—
—
0.9
—
0.9
Unit
kHz
ms
µs
µs
µs
µs
ns
ns
ns
ns
µs
µs
µs
µs
16
Rev. 1.0