C8051F330_07 Datasheet, PDF (81/216 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F330/1/2/3/4/5
9.2.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set. Table 9.2 lists the SFRs imple-
mented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 9.3, for a detailed description of each register.
Table 9.2. Special Function Register (SFR) Memory Map
F8 SPI0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0
F0
B
P0MDIN P1MDIN
EIP1
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2
E0 ACC
XBR0
XBR1 OSCLCN IT01CF
EIE1
D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2
D0 PSW REF0CN
P0SKIP P1SKIP
C8 TMR2CN
TMR2RLL TMR2RLH TMR2L TMR2H
C0 SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH
B8
IP
IDA0CN AMX0N AMX0P ADC0CF ADC0L ADC0H
B0
OSCXCN OSCICN OSCICL
FLSCL
A8
IE
CLKSEL EMI0CN
A0 P2
SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT
98 SCON0 SBUF0
CPT0CN
CPT0MD
90 P1
TMR3CN TMR3RLL TMR3RLH TMR3L TMR3H IDA0L
88 TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
80 P0
SP
DPL
DPH
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
(bit addressable)
VDM0CN
RSTSRC
FLKEY
CPT0MX
IDA0H
PSCTL
PCON
7(F)
Rev. 1.5
81