C8051F330_07 Datasheet, PDF (43/216 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F330/1/2/3/4/5
5. 10-Bit ADC (ADC0, C8051F330/2/4 only)
The ADC0 subsystem for the C8051F330/2/4 consists of two analog multiplexers (referred to collectively
as AMUX0) with 16 total input selections, and a 200 ksps, 10-bit successive-approximation-register ADC
with integrated track-and-hold and programmable window detector. The AMUX0, data conversion modes,
and window detector are all configurable under software control via the Special Function Registers shown
in Figure 5.1. ADC0 operates in both Single-ended and Differential modes, and may be configured to mea-
sure Ports0-1, the Temperature Sensor output, or V_DD with respect to Ports0-1 or GND. The ADC0 sub-
system is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The
ADC0 subsystem is in low power shutdown when this bit is logic 0.
P0.0
P0.7
P1.0
Temp
Sensor
P1.7
VDD
P0.0
P0.7
P1.0
P1.7
VREF
GND
18-to-1
AMUX
AMX0P
18-to-1
AMUX
AMX0N
ADC0CN
VDD
000
Start
Conversion ⁰⁰¹
010
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
011
Timer 1 Overflow
100
CNVSTR Input
10-Bit
(+)
SAR
101
Timer 3 Overflow
(-)
ADC
ADC0CF
ADC0LTH ADC0LTL
ADC0GTH ADC0GTL
AD0WINT
Window
Compare
32 Logic
Figure 5.1. ADC0 Functional Block Diagram
5.1. Analog Multiplexer
AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the
positive input: Ports0-1, the on-chip temperature sensor, or the positive power supply (V_DD). Any of the fol-
lowing may be selected as the negative input: Ports0-1, V_REF, or GND. When GND is selected as the
negative input, ADC0 operates in Single-ended Mode; all other times, ADC0 operates in Differential
Mode. The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in SFR
Definition 5.1 and SFR Definition 5.2.
The conversion code format differs between Single-ended and Differential modes. The registers ADC0H
and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion
of each conversion. Data can be right-justified or left-justified, depending on the setting of the AD0LJST.
When in Single-ended Mode, conversion codes are represented as 10-bit unsigned integers. Inputs are
Rev. 1.5
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