C8051F330_07 Datasheet, PDF (67/216 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F330/1/2/3/4/5
8. Comparator0
C8051F330/1/2/3/4/5 devices include an on-chip programmable voltage comparator, Comparator0, shown
in Figure 8.1.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asyn-
chronous “raw” output (CP0A). The asynchronous CP0A signal is available even when in when the system
clock is not active. This allows the Comparator to operate and generate an output with the device in STOP
mode. When assigned to a Port pin, the Comparator output may be configured as open drain or push-pull
(see Section “14.2. Port I/O Initialization” on page 129). Comparator0 may also be used as a reset
source (see Section “10.5. Comparator0 Reset” on page 102).
The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 8.2). The CMX0P1–
CMX0P0 bits select the Comparator0 positive input; the CMX0N1–CMX0N0 bits select the Comparator0
negative input. Important Note About Comparator Inputs: The Port pins selected as comparator inputs
should be configured as analog inputs in their associated Port configuration register, and configured to be
skipped by the Crossbar (for details on Port configuration, see Section “14.3. General Purpose Port I/O”
on page 131).
CMX0N3
CMX0N2
CMX0N1
CMX0N0
CMX0P3
CMX0P2
CMX0P1
CMX0P0
P0.0
P0.2
P0.4
P0.6
P1.0
P1.2
P1.4
P1.6
P0.1
P0.3
P0.5
P0.7
P1.1
P1.3
P1.5
P1.7
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
VDD
CP0 +
CP0 -
+
-
GND
D ^SET Q
Q
CLR
D ^SET Q
Q
CLR
(SYNCHRONIZER)
Reset
Decision
Tree
CP0
Crossbar
CP0A
0
CP0RIF
1
0
CP0FIF
1
CP0EN
EA
0
1
CP0
0 Interrupt
1
CP0RIE
CP0FIE
CP0MD1
CP0MD0
Figure 8.1. Comparator0 Functional Block Diagram
Rev. 1.5
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