C8051F330_07 Datasheet, PDF(101/216 Page) Silicon Laboratories

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C8051F330_07 Datasheet, PDF (101/216 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

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C8051F330/1/2/3/4/5

Important Note: The VDD monitor must be enabled before it is selected as a reset source. Selecting the

VDD monitor as a reset source before it is enabled and stabilized may cause a system reset. The proce-

dure for configuring the VDD monitor as a reset source is shown below:

Step 1. Enable the VDD monitor (VDMEN bit in VDM0CN = â1â).

Step 2. Wait for the VDD monitor to stabilize (see Table 10.1 for the VDD Monitor turn-on time).

Step 3. Select the VDD monitor as a reset source (PORSF bit in RSTSRC = â1â).

See Figure 10.2 for VDD monitor timing; note that the reset delay is not incurred after a VDD monitor reset.

See Table 10.1 for complete electrical characteristics of the VDD monitor.

SFR Definition 10.1. VDM0CN: VDD Monitor Control

R/W

VDMEN

Bit7

Reset Value

VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved Variable

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xFF

Bit7:

Bit6:

Bits5â0:

VDMEN: VDD Monitor Enable.

This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system resets

until it is also selected as a reset source in register RSTSRC (SFR Definition 10.2). The VDD

Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the

VDD monitor as a reset source before it has stabilized may generate a system reset.

See Table 10.1 for the minimum VDD Monitor turn-on time.

0: VDD Monitor Disabled.

1: VDD Monitor Enabled.

VDD STAT: VDD Status.

This bit indicates the current power supply status (VDD Monitor output).

0: VDD is at or below the VDD monitor threshold.

1: VDD is above the VDD monitor threshold.

Reserved. Read = 000000b. Write = donât care.

10.3. External Reset

The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-

ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST

pin may be necessary to avoid erroneous noise-induced resets. See Table 10.1 for complete RST pin

specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.

10.4. Missing Clock Detector Reset

The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system

clock remains high or low for more than 100 Âµs, the one-shot will time out and generate a reset. After a

MCD reset, the MCDRSF flag (RSTSRC.2) will read â1â, signifying the MCD as the reset source; otherwise,

this bit reads â0â. Writing a â1â to the MCDRSF bit enables the Missing Clock Detector; writing a â0â disables

it. The state of the RST pin is unaffected by this reset.

Rev. 1.5

101

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