C8051F330_07 Datasheet, PDF (26/216 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F330/1/2/3/4/5
1.4. Programmable Digital I/O and Crossbar
C8051F330/1/2/3/4/5 devices include 17 I/O pins (two byte-wide Ports and one 1-bit-wide Port). The
C8051F330/1/2/3/4/5 Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be
configured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be config-
ured for push-pull or open-drain output. The “weak pullups” that are fixed on typical 8051 devices may be
globally disabled, providing power savings capabilities.
The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins. (See
Figure 1.11.) On-chip counter/timers, serial buses, HW interrupts, comparator output, and other digital sig-
nals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar Control
registers. This allows the user to select the exact mix of general purpose Port I/O and digital resources
needed for the particular application.
XBR0, XBR1,
PnSKIP Registers
PnMDOUT,
PnMDIN Registers
Highest
Priority
Lowest
Priority
2
UART
4
SPI
2
SMBus
CP0
2
Outputs
SYSCLK
PCA
4
2
T0, T1
8
P0 _(P0.0-P0.7)
8
P1 _(P1.0-P1.7)
Priority
Decoder
8
P0
I/O
Cells
P0.0
P0.7
Digital
Crossbar
8
P1
I/O
Cells
P1.0
P1.7
Figure 1.11. Digital Crossbar Diagram
1.5. Serial Ports
The C8051F330/1/2/3/4/5 Family includes an SMBus/I²C interface, a full-duplex UART with enhanced
baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in
hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
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Rev. 1.5