C8051F330_07 Datasheet, PDF (192/216 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F330/1/2/3/4/5
18.3.2. 8-bit Timers with Auto-Reload
When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 18.7. TMR3RLL holds the reload value for TMR3L; TMR3RLH
holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select either SYSCLK or
the clock defined by the Timer 3 External Clock Select bit (T3XCLK in TMR3CN), as follows:
T3MH
0
0
1
T3XCLK
0
1
X
TMR3H Clock
Source
SYSCLK / 12
External Clock / 8
SYSCLK
T3ML
0
0
1
T3XCLK
0
1
X
TMR3L Clock
Source
SYSCLK / 12
External Clock / 8
SYSCLK
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H over-
flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
T3XCLK
SYSCLK / 12
0
External Clock / 8
1
SYSCLK
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL
10
TMR3RLH ^Reload
0
TR3
TCLK
TMR3H
1
TMR3RLL ^Reload
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
T3XCLK
1
TCLK _TMR3L
To ADC
0
Figure 18.7. Timer 3 8-Bit Mode Block Diagram
Interrupt
192
Rev. 1.5