C8051F330_07 Datasheet, PDF (214/216 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F330/1/2/3/4/5
DOCUMENT CHANGE LIST
Revision 1.4 to Revision 1.5
• Updated Table 3.1 - Added supply current data from characterization.
• Updated Table 5.1 - Added MIN/MAX numbers for ADC Offset and Full Scale Error.
• Fixed SFR Definition 8.2 - Typo in bit descriptions - “2-0” changed to “3-0”.
• Fixed SFR Definition 9.4 - Text at bottom of figure was cut off.
• Added Section “11.4. Flash Write and Erase Guidelines” on page 109.
• Fixed Section “12. External RAM” on page 113, paragraph 2 - Typo in description - “upper 6-bits”
changed to “upper 7 bits”.
• Fixed text in Section “19.3.2. Watchdog Timer Usage” on page 205 to read “256 PCA clock cycles,
or 3072 system clock cycles”.
• Changed Table 19.4, Note 2 to refer to SYSCLK reset frequency = Internal Oscillator / 8.
• Fixed Equation 19.6, “Watchdog Timer Offset in PCA Clocks,” - Typo in equation - “PCA0CPL4”
changed to “PCA0CPL2”.
Revision 1.3 to Revision 1.4
• Removed references to C8051F330D throughout the data sheet because the 'F330D device is func-
tionally identical to the C8051F330 device (these two part numbers differ by package type only).
• Updated titles of Chapters 5, 6, and 7 to show supported devices.
• Updated Table 1.1, “Product Selection Guide,” on page 18.
- Added ordering part number information for lead-free parts.
• Added Table 3.2, “Index to Electrical Characteristics Tables,” on page 34
• Added Table 11.2, “Flash Security Summary,” on page 108 for clarity, replacing the Flash security sum-
maries text.
214
Rev. 1.5