C8051F330_07 Datasheet, PDF (163/216 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F330/1/2/3/4/5
Table 16.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz
Oscillator
Frequency: 22.1184 MHz
Target Baud Rate Oscilla- Timer Clock
Baud Rate % Error tor Divide Source
(bps)
Factor
SCA1–SCA0
(pre-scale
select)¹
T1M^{1 Timer 1}
Reload
Value (hex)
230400
0.00%
96
SYSCLK
XX²
1
0xD0
115200
0.00%
192
SYSCLK
XX
1
0xA0
57600
0.00%
384
SYSCLK
XX
1
0x40
28800
0.00%
768 SYSCLK / 12
00
0
0xE0
14400
0.00%
1536 SYSCLK / 12
00
0
0xC0
9600
0.00%
2304 SYSCLK / 12
00
0
0xA0
2400
0.00%
9216 SYSCLK / 48
10
0
0xA0
1200
0.00%
18432 SYSCLK / 48
10
0
0x40
230400
0.00%
96
EXTCLK / 8
11
0
0xFA
115200
0.00%
192 EXTCLK / 8
11
0
0xF4
57600
0.00%
384 EXTCLK / 8
11
0
0xE8
28800
0.00%
768 EXTCLK / 8
11
0
0xD0
14400
0.00%
1536 EXTCLK / 8
11
0
0xA0
9600
0.00%
2304 EXTCLK / 8
11
0
0x70
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 18.1.
2. X = Don’t care.
Table 16.4. Timer Settings for Standard Baud Rates Using an External 18.432 MHz
Oscillator
Frequency: 18.432 MHz
Target Baud Rate Oscilla- Timer Clock
Baud Rate % Error tor Divide Source
(bps)
Factor
SCA1–SCA0
(pre-scale
select)¹
T1M^{1 Timer 1}
Reload
Value (hex)
230400
0.00%
80
SYSCLK
XX²
1
0xD8
115200
0.00%
160
SYSCLK
XX
1
0xB0
57600
0.00%
320
SYSCLK
XX
1
0x60
28800
0.00%
640 SYSCLK / 4
01
0
0xB0
14400
0.00%
1280 SYSCLK / 4
01
0
0x60
9600
0.00%
1920 SYSCLK / 12
00
0
0xB0
2400
0.00%
7680 SYSCLK / 48
10
0
0xB0
1200
0.00%
15360 SYSCLK / 48
10
0
0x60
230400
0.00%
80
EXTCLK / 8
11
0
0xFB
115200
0.00%
160 EXTCLK / 8
11
0
0xF6
57600
0.00%
320 EXTCLK / 8
11
0
0xEC
28800
0.00%
640 EXTCLK / 8
11
0
0xD8
14400
0.00%
1280 EXTCLK / 8
11
0
0xB0
9600
0.00%
1920 EXTCLK / 8
11
0
0x88
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 18.1.
2. X = Don’t care.
Rev. 1.5
163