C8051F330_07 Datasheet, PDF (62/216 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F330/1/2/3/4/5
SFR Definition 6.3. IDA0L: IDA0 Data Word LSB
R/W
R/W
R
R
R
R
R
R
Reset Value
—
—
—
—
—
— 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0x96
Bits 7–6: IDA0 Data Word Low-Order Bits.
Lower 2 bits of the 10-bit Data Word.
Bits 5–0: UNUSED. Read = 000000b, Write = don’t care.
Table 6.1. IDAC Electrical Characteristics
–40 to +85 °C, V_DD = 3.0 V Full-scale output current set to 2 mA unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Static Performance
Resolution
10
Units
bits
Integral Nonlinearity
—
±0.5
—
LSB
Differential Nonlinearity Guaranteed Monotonic
—
±0.5
±1
LSB
Output Compliance Range
—
Output Noise
I_OUT = 2 mA; R_LOAD = 100 Ω
—
Offset Error
—
Full Scale Error
2 mA Full Scale Output
Current
—
Full Scale Error Tempco
—
V_DD Power Supply
—
Rejection Ratio
Output Capacitance
—
Dynamic Performance
Output Settling Time to 1/2
LSB
IDA0H:L = 0x3FF to 0x000
—
Startup Time
—
— V_DD – 1.2 V
1
—
nA/rtHz
0
—
LSB
0
—
LSB
30
—
ppm/°C
52
—
dB
2
—
pF
5
—
µs
5
—
µs
Gain Variation
1 mA Full Scale Output Current
—
±1
—
%
0.5 mA Full Scale Output Current
—
±1
—
%
Power Consumption
Power Supply Current (V_DD
2 mA Full Scale Output Current
1 mA Full Scale Output Current
—
2100
—
—
1100
—
µA
µA
supplied to IDAC)
0.5 mA Full Scale Output Current
—
600
—
µA
62
Rev. 1.5