C8051F330_07 Datasheet, PDF (71/216 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F330/1/2/3/4/5
SFR Definition 8.3. CPT0MD: Comparator0 Mode Selection
R
R
R/W
R/W
R
R
R/W
R/W
Reset Value
-
-
CP0RIE CP0FIE
-
-
CP0MD1 CP0MD0 00000010
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0x9D
Bits7–6:
Bit5:
Bit4:
Bits3–2:
Bits1–0:
UNUSED. Read = 00b, Write = don’t care.
CP0RIE: Comparator0 Rising-Edge Interrupt Enable.
0: Comparator0 Rising-edge interrupt disabled.
1: Comparator0 Rising-edge interrupt enabled.
CP0FIE: Comparator0 Falling-Edge Interrupt Enable.
0: Comparator0 Falling-edge interrupt disabled.
1: Comparator0 Falling-edge interrupt enabled.
UNUSED. Read = 00b, Write = don’t care.
CP0MD1–CP0MD0: Comparator0 Mode Select
These bits select the response time for Comparator0.
Mode
0
1
2
3
CP0MD1 CP0MD0
0
0
0
1
1
0
1
1
CP0 Response Time
(TYP)
100 ns
175 ns
320 ns
1050 ns
Rev. 1.5
71