C8051F330_07 Datasheet, PDF (104/216 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F330/1/2/3/4/5
Table 10.1. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
RST Output Low Voltage
RST Input High Voltage
RST Input Low Voltage
RST Input Pullup Current
V_DD POR Threshold (V_RST)
Missing Clock Detector Time-
out
Reset Time Delay
Minimum RST Low Time to
Generate a System Reset
V_DD Monitor Turn-on Time
V_DD Monitor Supply Current
Conditions
I_OL = 8.5 mA,
V_DD = 2.7 V to 3.6 V
RST = 0.0 V
Time from last system clock
rising edge to reset initiation
Delay between release of any
reset source and code
execution at location 0x0000
Min
—
0.7 x V_DD
—
—
2.40
100
5.0
15
100
—
Typ
—
—
—
25
2.55
220
—
—
—
20
Max Units
0.6
V
—
V
0.3 x V_DD
40
µA
2.70
V
600
µs
—
µs
—
µs
—
µs
50
µA
104
Rev. 1.5