C8051F330_07 Datasheet, PDF (125/216 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F330/1/2/3/4/5
14. Port Input/Output
Digital and analog resources are available through 17 I/O pins. Port pins are organized as two byte-wide
Ports and one 1-bit Port. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog
input; Port pins P0.0 - P1.7 can be assigned to one of the internal digital resources as shown in
Figure 14.3. The designer has complete control over which functions are assigned, limited only by the
number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority
Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch,
regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 14.3 and Figure 14.4). The registers XBR0 and XBR1, defined in SFR Definition 14.1 and SFR
Definition 14.2, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 14.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete
Electrical Specifications for Port I/O are given in Table 14.1 on page 136.
XBR0, XBR1,
PnSKIP Registers
PnMDOUT,
PnMDIN Registers
Highest
Priority
Lowest
Priority
2
UART
4
SPI
2
SMBus
CP0
2
Outputs
SYSCLK
PCA
4
2
T0, T1
8
P0 _(P0.0-P0.7)
8
P1 _(P1.0-P1.7)
Priority
Decoder
8
P0
I/O
Cells
P0.0
P0.7
Digital
Crossbar
8
P1
I/O
Cells
P1.0
P1.7
Figure 14.1. Port I/O Functional Block Diagram
Rev. 1.5
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