C8051F330_07 Datasheet, PDF (164/216 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F330/1/2/3/4/5
Table 16.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz
Oscillator
Frequency: 11.0592 MHz
Target Baud Rate Oscilla- Timer Clock
Baud Rate % Error tor Divide Source
(bps)
Factor
SCA1–SCA0
(pre-scale
select)¹
T1M^{1 Timer 1}
Reload
Value (hex)
230400
0.00%
48
SYSCLK
XX²
1
0xE8
115200
0.00%
96
SYSCLK
XX
1
0xD0
57600
0.00%
192
SYSCLK
XX
1
0xA0
28800
0.00%
384
SYSCLK
XX
1
0x40
14400
0.00%
768 SYSCLK / 12
00
0
0xE0
9600
0.00%
1152 SYSCLK / 12
00
0
0xD0
2400
0.00%
4608 SYSCLK / 12
00
0
0x40
1200
0.00%
9216 SYSCLK / 48
10
0
0xA0
230400
0.00%
48
EXTCLK / 8
11
0
0xFD
115200
0.00%
96
EXTCLK / 8
11
0
0xFA
57600
0.00%
192 EXTCLK / 8
11
0
0xF4
28800
0.00%
384 EXTCLK / 8
11
0
0xE8
14400
0.00%
768 EXTCLK / 8
11
0
0xD0
9600
0.00%
1152 EXTCLK / 8
11
0
0xB8
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 18.1.
2. X = Don’t care.
Table 16.6. Timer Settings for Standard Baud Rates Using an External 3.6864 MHz
Oscillator
Frequency: 3.6864 MHz
Target
Baud Rate
(bps)
Baud
Rate%
Error
Oscilla- Timer Clock
tor Divide Source
Factor
SCA1–SCA0
(pre-scale
select)¹
T1M^{1 Timer 1}
Reload
Value (hex)
230400
0.00%
16
SYSCLK
XX²
1
0xF8
115200
0.00%
32
SYSCLK
XX
1
0xF0
57600
0.00%
64
SYSCLK
XX
1
0xE0
28800
0.00%
128
SYSCLK
XX
1
0xC0
14400
0.00%
256
SYSCLK
XX
1
0x80
9600
0.00%
384
SYSCLK
XX
1
0x40
2400
0.00%
1536 SYSCLK / 12
00
0
0xC0
1200
0.00%
3072 SYSCLK / 12
00
0
0x80
230400
0.00%
16
EXTCLK / 8
11
0
0xFF
115200
0.00%
32
EXTCLK / 8
11
0
0xFE
57600
0.00%
64
EXTCLK / 8
11
0
0xFC
28800
0.00%
128 EXTCLK / 8
11
0
0xF8
14400
0.00%
256 EXTCLK / 8
11
0
0xF0
9600
0.00%
384 EXTCLK / 8
11
0
0xE8
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 18.1.
2. X = Don’t care.
164
Rev. 1.5